参数资料
| 型号： | EP9315-IBZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 78/106页 |
| 文件大小： | 0K |
| 描述： | IC ARM9 SOC ENH UNIV 352PBGA |
| 标准包装： | 40 |
| 系列： | EP9 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 连通性： | EBI/EMI，EIDE，以太网，I²C，IrDA，键盘/触摸屏，PCMCIA，SPI，UART/USART，USB |
| 外围设备： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 32K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 352-BGA |
| 包装： | 托盘 |
| 配用： | 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9 |
| 其它名称： | 598-1263 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页当前第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
DS785UM1
3-3
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
Inexact
Note that the division by zero exception is not supported as the MaverickCrunch co-
processor does not provide division or square root.
3.1.3 Pipelines and Latency
There are two primary pipelines within the MaverickCrunch co-processor. One handles all
communication with the ARM920T, while the other, the “data path” pipeline, handles all
arithmetic operations (this one actually operates at one half the MaverickCrunch co-
processor clock frequency).
The data path pipeline may run synchronously or asynchronously with respect to the ARM
instruction pipeline. If run asynchronously, data path computation is decoupled from the ARM,
allowing high throughput, though arithmetic exceptions are not synchronous. If run
synchronously, exceptions are synchronous, but throughput suffers.
Assuming no inter-instruction dependencies causing pipeline stalls, arithmetic instructions
can produce a new result every two ARM920T clocks, which is a maximum throughput of one
data path instruction per eight ARM920T clocks. The only exception is 64-bit multiplies
(CFMULD or CFMUL64), which require six extra ARM920T clocks to produce their result,
which is maximum throughput of eight ARM920T clocks per instruction.
The normal latency for an arithmetic instruction is approximately nine ARM920T clocks, from
initial decode to the time the result is written to the register file. A 64-bit multiply requires 15
clocks.
3.1.4 Data Registers
The MaverickCrunch co-processor contains these registers:
Sixteen 64-bit general purpose registers, c0 through c15
Four 72-bit accumulators, a0 through a3
One status and control register, DSPSC
A single precision floating point value is stored in the upper 32 bits of a 64-bit register and
must be explicitly promoted to double precision to be used in double precision calculations:
Opcode
63
62
55
32 31
0
Sign Exponent
Significand
not used
相关PDF资料 |
PDF描述 |
|---|---|
| EP9315-IB | IC ARM920T MCU 200MHZ 352-PBGA |
| EPC1064LI20 | IC CONFIG DEVICE 65KBIT 20-PLCC |
| EPC16UC88AA | IC CONFIG DEVICE 16MBIT 88-UBGA |
| EPCS16SI16N | IC CONFIG DEVICE 16MBIT 16-SOIC |
| EPF10K10AQI208-3 | IC FLEX 10KA FPGA 10K 208-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP9316 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
| EP9317 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
| EP9318 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
| EP9319 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
| EP9320 | 制造商:PCA 制造商全称:PCA ELECTRONICS INC. 功能描述:14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines |
发布紧急采购，3分钟左右您将得到回复。