参数资料
型号: EP9315-IBZ
厂商: Cirrus Logic Inc
文件页数: 91/106页
文件大小: 0K
描述: IC ARM9 SOC ENH UNIV 352PBGA
标准包装: 40
系列: EP9
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 200MHz
连通性: EBI/EMI,EIDE,以太网,I²C,IrDA,键盘/触摸屏,PCMCIA,SPI,UART/USART,USB
外围设备: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
输入/输出数: 16
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 352-BGA
包装: 托盘
配用: 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名称: 598-1263
DS785UM1
3-15
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format.
The remaining bits in the instruction formats are interpreted as follows:
opcode1: MaverickCrunch co-processor-defined opcode
opcode2: MaverickCrunch co-processor defined opcode
CRn: MaverickCrunch co-processor-defined register
CRd: MaverickCrunch co-processor-defined register
CRm: MaverickCrunch co-processor-defined register
Rn: Specifies an ARM base address register. These bits are ignored by the
MaverickCrunch co-processor.
Rd: Specifies a source or destination ARM register
cp_num: Co-processor number
P: Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the
MaverickCrunch co-processor.
U: Specifies whether the supplied 8-bit offset is added to a base register (U=1) or
subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co-
processor.
N: Specifies the width of a data type involved in a move operation. The MaverickCrunch
Table 3-5. Condition Code Definitions
Cond
[31:28]
Mnemonic
Extension
Meaning
Status Flag State
0000
EQ
Equal
Z set
0001
NE
Not Equal
Z clear
0010
CS/HS
Carry Set/Unsigned Higher or Same
C set
0011
CC/LO
Carry Clear/Unsigned Lower
C clear
0100
MI
Minus/Negative
N set
0101
PL
Plus/Positive or Zero
N clear
0110
VS
Overflow
V set
0111
VC
No Overflow
V clear
1000
HI
Unsigned Higher
C set and Z clear
1001
LS
Unsigned Lower or Same
C clear or Z set
1010
GE
Signed Greater Than or Equal
N set and V set, or N clear and V clear (N = V)
1011
LT
Signed Less Than
N set and V clear, or N clear and V set (N ! = V)
1100
GT
Signed Greater Than
Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
1101
LE
Signed Less Than or Equal
Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
1110
AL
Always (unconditional)
-
1111
NV
Never
-
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