- 您现在的位置：买卖IC网 > PDF目录362743 > EP9315 (Cirrus Logic, Inc.) Enhanced Universal Platform System-on-Chip Processor PDF资料下载
参数资料
| 型号： | EP9315 |
| 厂商： | Cirrus Logic, Inc. |
| 英文描述： | Enhanced Universal Platform System-on-Chip Processor |
| 中文描述： | 增强型通用平台上系统芯片处理器 |
| 文件页数： | 7/64页 |
| 文件大小： | 1031K |
| 代理商： | EP9315 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
DS638PP4
Copyright 2005 Cirrus Logic (All Rights Reserved)
7
EP9315
Enhanced Universal Platform SOC Processor
IDE Interface
The IDE Interface provides an industry-standard
connection to two AT Advanced Packet Interface (ATAPI)
compliant devices. The IDE port will attach to a master
and a slave device. The internal DMA controller performs
all data transfers using the Ultra DMA modes. The
interface supports the following operating modes:
PIO Mode 0 thru 4
Ultra DMA Modes 0 thru 3
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Serial Interfaces (SPI, I
2
S and AC ’97)
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor
, Motorola
and
Texas Instruments
signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. Three I
2
S ports
can be configured to support six channel 24-bit audio.
These ports are multiplexed so that I
2
S port 0 will take
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
Normal Mode: One SPI Port and one AC’97 Port
I
2
S on SSP Mode: One AC’97 Port and up to three I
2
S
Ports
I
2
S on AC’97 Mode: One SPI Port and up to three I
2
S
Ports
Raster / LCD Interface
The Raster / LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast. LCD specific features include:
Table C. IDE Interface Pin Assignments
Pin Mnemonic
Pin Description
DD[15-0]
IDE Data bus
IDEDA[2-0]
IDE Device address
IDECSn[0,1]
IDE Chip Select 0 and 1
DIORn
IDE Read Strobe
DIOWn
IDE Write Strobe
DMACKn
IDE DMA acknowledge
Table D. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic
Pin Description
MDC
Management Data Clock
MDIO
Management Data I/O
RXCLK
Receive Clock
MIIRXD[3:0]
Receive Data
RXDVAL
Receive Data Valid
RXERR
Receive Data Error
TXCLK
Transmit Clock
MIITXD[3:0]
Transmit Data
TXEN
Transmit Enable
TXERR
Transmit Error
CRS
Carrier Sense
CLD
Collision Detect
Table E. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I2S on SSP
Mode
I2S on AC'97
Mode
Pin
Description
Pin Description
Pin Description
SCLK1
SPI Bit Clock
I2S Serial Clock
SPI Bit Clock
SFRM1
SPI Frame Clock I2S Frame Clock
SPI Frame Clock
SSPRX1
SPI Serial Input
I2S Serial Input
SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output
SPI Serial Output
(No I2S Master
Clock)
ARSTn
AC'97 Reset
AC'97 Reset
I2S Master Clock
ABITCLK AC'97 Bit Clock
AC'97 Bit Clock
I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input
I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial
Output
I2S Serial Output
相关PDF资料 |
PDF描述 |
|---|---|
| EP9315-CB | Enhanced Universal Platform System-on-Chip Processor |
| EP9315-CBZ | Enhanced Universal Platform System-on-Chip Processor |
| EPA480C-SOT89 | DC-6GHz High Efficiency Heterojunction Power FET |
| EPA480 | DC-6GHz High Efficiency Heterojunction Power FET |
| EPB025A | Low Noise High Gain Heterojunction FET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP9315A-Z | 制造商:Cirrus Logic 功能描述:- Bulk |
| EP9315CB | 制造商:Cirrus Logic 功能描述: |
| EP9315-CB | 功能描述:微处理器 - MPU IC Universal Platfrm ARM9 SOC Prcessor RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| EP9315CB/E0 | 制造商:Cirrus Logic 功能描述: |
| EP9315CB/E1 | 制造商:Cirrus Logic 功能描述: |
发布紧急采购，3分钟左右您将得到回复。