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参数资料
| 型号： | EPC1213PI8 |
| 厂商： | Altera |
| 文件页数： | 3/26页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 212KBIT 8-DIP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 100 |
| 系列： | EPC |
| 可编程类型： | OTP |
| 存储容量： | 212kb |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 配用： | PLMJ1213-ND - PROGRAMMER ADAPTER 20 PIN J-LEAD |
| 其它名称： | 544-1370-5 EPC1213PI8-ND |
Power and Operation
Page 11
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
logic level for VCCSEL and VPPSEL pins. A high logic level means the pin should be
connected to VCC, while a low logic level means the pin should be connected to GND.
At a 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except for DATA, DCLK, and
nCASC
pins. The DATA and DCLK pins are used only to interface between the EPC2
device and the FPGA it is configuring. Table 4 lists the voltage tolerences of all EPC2
device pins.
If one EPC1, EPC2, or EPC1441 configuration device is powered at 3.3 V, the nSTATUS
and CONF_DONE pull-up resistors must be connected to 3.3 V. If these configuration
devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors can be
connected to either 3.3 V or 5.0 V.
Table 3. VCCSEL and VPPSEL Pin Functions on the EPC2 Device
VCC Voltage Level
(V)
VPP Voltage Level
(V)
VCCSEL Pin Logic
Level
VPPSEL Pin Logic
Level
3.3
High
3.3
5.0
High
Low
5.0
Low
Table 4. EPC2 Device Input and Bidirectional Pin Voltage Tolerance
Pin
5.0-V Operation
3.3-V Operation
5.0-V Tolerant
3.3-V Tolerant
5.0-V Tolerant
3.3-V Tolerant
DATA
vv
—
v
DCLK
vv
—
v
nCASC
vv
—
v
OE
vvvv
nCS
vvvv
VCCSEL
vvvv
VPPSEL
vvvv
nINIT_CONF
vvvv
TDI
vvvv
TMS
vvvv
TCK
vvvv
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