参数资料
型号: EPCS4SI8N
厂商: Altera
文件页数: 23/40页
文件大小: 0K
描述: IC CONFIG DEVICE 4MBIT 8-SOIC
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 100
系列: EPCS
可编程类型: 系统内可编程
存储容量: 4Mb
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 604 (CN2011-ZH PDF)
其它名称: 544-1379-5
EPCS4SI8N-ND
Active Serial FPGA Configuration
Page 3
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Figure 1 shows the EPCS device block diagram.
Accessing Memory in EPCS Devices
You can access the unused memory locations of the EPCS device to store or retrieve
data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for
creating bus-based (especially microprocessor-based) systems in Altera devices.
SOPC Builder assembles library components such as processors and memories into
custom microprocessor systems.
SOPC Builder includes the EPCS device controller core, which is an interface core
designed specifically to work with the EPCS device. With this core, you can create a
system with a Nios embedded processor that allows software access to any memory
location within the EPCS device.
Active Serial FPGA Configuration
The following Altera FPGAs support the AS configuration scheme with EPCS devices:
Arria series
Cyclone series
All device families in the Stratix series except the Stratix device family
There are four signals on the EPCS device that interface directly with the FPGA’s
control signals. The EPCS device signals are DATA, DCLK, ASDI, and nCS interface with
the DATA0, DCLK, ASDO, and nCSO control signals on the FPGA, respectively.
1 For more information about the EPCS device pin description, refer to Table 23 on
Figure 1. EPCS Device Block Diagram
Control
Logic
I/O Shift
Register
Memory
Array
Status Register
Address Counter
Decode Logic
Data Buffer
nCS
DCLK
DATA
ASDI
EPCS Device
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