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参数资料
| 型号： | EPF6016A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 13/59页 |
| 文件大小： | 1051K |
| 代理商： | EPF6016A |
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Altera Corporation
13
FLEX 6000 Programmable Logic Device Family Data Sheet
Cascade Chain
The cascade chain enables the FLEX 6000 architecture to implement very
wide fan-in functions. Adjacent LUTs can be used to implement portions
of the function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical
AND
or logical
OR
gate (via De Morgan’s inversion) to connect the outputs of adjacent
LEs. Each additional LE provides four more inputs to the effective width
of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can
be created automatically by the MAX+PLUS II or Quartus Compiler
during design processing, or manually by the designer during design
entry. Parameterized functions such as LPM and DesignWare functions
automatically take advantage of cascade chains for the appropriate
functions.
A cascade chain implementing an
AND
gate can use the register in the last
LE; a cascade chain implementing an
OR
gate cannot use this register
because of the inversion required to implement the
OR
gate.
Because the first LE of an LAB can generate control signals for that LAB,
the first LE in each LAB is not included in cascade chains. Moreover,
cascade chains longer than nine bits are automatically implemented by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from an even-numbered LAB to another even-numbered
LAB, or from an odd-numbered LAB to another odd-numbered LAB. For
example, the last LE of the first LAB in a row cascades to the second LE of
the third LAB. The cascade chain does not cross the center of the row. For
example, in an EPF6016 device, the cascade chain stops at the 11th LAB in
a row and a new cascade chain begins at the 12th LAB.
Figure 6
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. In this example, functions of 4
n
variables are
implemented with
n
LEs. With the cascade chain, 3.4 ns are needed to
decode a 16-bit address.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6016AFC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3N | 制造商:Altera Corporation 功能描述: |
| EPF6016AFC256-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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