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参数资料
| 型号： | EPM3256AQC208-6 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 6 ns, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 12/43页 |
| 文件大小： | 716K |
| 代理商： | EPM3256AQC208-6 |
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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
...and More
Features
s
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
s
Programmable power-saving mode for a power reduction of over
50% in each macrocell
s
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
s
Programmable security bit for protection of proprietary designs
s
Enhanced architectural features, including:
–
6 pin- or logic-driven output enable signals
–
Two global clock signals with optional inversion
–
Enhanced interconnect resources for improved routability
–
Programmable output slew-rate control
s
Software design support and automatic place-and-route provided by
the Altera MAX+PLUS II development system for Windows-based
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and the QuartusTM development system
for Windows-based PCs and Sun SPARCstation and HP 9000
Series 700/800 workstations
s
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third-party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
s
Programming support with Altera’s Master Programming Unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from third-party manufacturers and
any in-circuit tester that supports JamTM Files (.jam), Jam Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low-cost, high-performance devices based on
Altera’s MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM-based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 192.3 MHz. MAX 3000A devices
in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2. See Table 2.
相关PDF资料 |
PDF描述 |
|---|---|
| EPM3256AQI208-6 | EE PLD, 6 ns, PQFP208 |
| EPM7128ABC100-6 | EE PLD, 6 ns, PBGA100 |
| EPM7128ABC100-7 | EE PLD, 7.5 ns, PBGA100 |
| EPM7128ABI100-10 | EE PLD, 10 ns, PBGA100 |
| EPM7128ABI100-12 | EE PLD, 12 ns, PBGA100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM3256AQC208-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQC208-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQI208-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AQI208-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256ATC100-5N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Higha??performance, lowa??cost CMOS EEPROMa??based programmable |
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