- 您现在的位置：买卖IC网 > PDF目录362753 > EPM3512A (Altera Corporation) Programmable Logic Device Family PDF资料下载
参数资料
| 型号： | EPM3512A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可编程逻辑器件系列 |
| 文件页数： | 2/42页 |
| 文件大小： | 649K |
| 代理商： | EPM3512A |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
2
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
■
■
■
■
PCI compatible
Bus–friendly architecture including programmable slew–rate control
Open–drain output option
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power–saving mode for a power reduction of over
50
%
in each macrocell
Configurable expander product–term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
Enhanced architectural features, including:
–
6 or 10 pin– or logic–driven output enable signals
–
Two global clock signals with optional inversion
–
Enhanced interconnect resources for improved routability
–
Programmable output slew–rate control
Software design support and automatic place–and–route provided
by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/ 800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with the Altera master programming unit
(MPU), MasterBlaster
TM
communications cable, ByteBlasterMV
TM
parallel port download cable, BitBlaster
TM
serial download cable as
well as programming hardware from third–party manufacturers and
any in–circuit tester that supports Jam
TM
Standard Test and
Programming Language (STAPL) Files (
.jam
), Jam STAPL Byte-Code
Files (
.jbc
), or Serial Vector Format Files (
.svf
)
■
■
■
■
■
■
■
General
Description
MAX 3000A devices are low–cost, high–performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM–based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG)
PCI Local Bus
Specification, Revision 2.2
. See
Table 2
.
相关PDF资料 |
PDF描述 |
|---|---|
| EPM5016 | High-Speed, High-Density MAX 5000 Devices |
| EPM5032 | High-Speed, High-Density MAX 5000 Devices |
| EPM5064 | High-Speed, High-Density MAX 5000 Devices |
| EPM5128 | High-Speed, High-Density MAX 5000 Devices |
| EPM5130 | High-Speed, High-Density MAX 5000 Devices |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM3512AFC25610 | 制造商:Altera Corporation 功能描述: |
| EPM3512AFC256-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3512AFC256-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3512AFC256-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3512AFC256-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
发布紧急采购，3分钟左右您将得到回复。