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参数资料
型号： EPM7096
厂商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可编程逻辑器件系列
文件页数： 1/62页
文件大小： 1173K
代理商： EPM7096
Altera Corporation
1
MAX 7000
Programmable Logic
Device Family
December 2002, ver. 6.5
Data Sheet
DS-MAX7000-6.5
Features...
■
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
–
ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX
7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
Tables 1
and
2
)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
■
■
■
■
■
■
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000A Programmable Logic Device Family
Data Sheet
or the
Sheet
.
Table 1. MAX 7000 Device Features
Feature
EPM7032
EPM7064
EPM7096
EPM7128E
EPM7160E
EPM7192E
EPM7256E
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
600
1,250
1,800
2,500
3,200
3,750
5,000
32
2
64
4
96
6
128
8
160
10
192
12
256
16
36
68
76
100
104
124
164
6
5
6
5
7.5
6
3
4.5
125.0
7.5
6
3
4.5
125.0
10
7
3
5
12
7
3
6
90.9
12
7
3
6
90.9
2.5
4
151.5
2.5
4
151.5
100.0
相关PDF资料
PDF描述
EPM7128E Programmable Logic Device Family
EPM7128S Programmable Logic Device Family
EPM7160E Programmable Logic Device Family
EPM7160S Programmable Logic Device Family
EPM7192E Programmable Logic Device Family
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参数描述
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EPM7096JC68-2 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC68-3 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC84 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP Complex PLD
EPM7096JC84-2 制造商:未知厂家 制造商全称:未知厂家 功能描述:UV-Erasable/OTP Complex PLD
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