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| 型号： | EPM7128EQI100-15 |
| 厂商： | Altera |
| 文件页数： | 21/66页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 128 100-PQFP |
| 标准包装： | 66 |
| 系列： | MAX® 7000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 4.5 V ~ 5.5 V |
| 逻辑元件/逻辑块数目： | 8 |
| 宏单元数： | 128 |
| 门数： | 2500 |
| 输入/输出数： | 84 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-PQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 544-2324-5 |
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28
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than
20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
VCC must rise monotonically.
(5)
The POR time for all 7000S devices does not exceed 300 μs. The sufficient VCCINT voltage level for POR is 4.5 V. The
device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.
(6)
3.3-V I/O operation is not available for 44-pin packages.
(7)
The VCCISP parameter applies only to MAX 7000S devices.
(8)
During in-system programming, the minimum DC input voltage is –0.3 V.
(9)
These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26.
(10) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(11) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL, PCI, or CMOS output current.
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
–60 μA.
(13) Capacitance is measured at 25° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF.
Figure 11 shows the typical output drive characteristics of MAX 7000
devices.
Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices
Timing Model
MAX 7000 device timing can be analyzed with the Altera software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 12. MAX 7000
devices have fixed internal delays that enable the designer to determine
the worst-case timing of any design. The Altera software provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 3.3 V
IOL
IOH
Room Temperature
3.3
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 5.0 V
IOL
IOH
Room Temperature
I O
Typical
Output
Current (mA)
I O
Typical
Output
Current (mA)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7128EQI10020 | 制造商:ALTERA 功能描述:NEW |
| EPM7128EQI100-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128LC84-12 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 128-CELL, 12NS PROP DELAY, 84 Pin, Plastic, PLCC |
| EPM7128LC84-15 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 128-CELL, 15NS PROP DELAY, 84 Pin, Plastic, PLCC |
| EPM7128QC1004 | 制造商:ALTERA 功能描述:* |
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