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| 型号： | EPM7128EQI100-15 |
| 厂商： | Altera |
| 文件页数： | 56/66页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 128 100-PQFP |
| 标准包装： | 66 |
| 系列： | MAX® 7000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 4.5 V ~ 5.5 V |
| 逻辑元件/逻辑块数目： | 8 |
| 宏单元数： | 128 |
| 门数： | 2500 |
| 输入/输出数： | 84 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-PQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 544-2324-5 |
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Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices contain from 32 to 256 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals are switching. The output drivers of all MAX 7000 devices (except
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.
The MAX 7000 family is supported byAltera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The software runs
on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series
700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 7000 architecture includes the following elements:
■
Logic array blocks
■
Macrocells
■
Expander product terms (shareable and parallel)
■
Programmable interconnect array
■
I/O control blocks
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7128EQI10020 | 制造商:ALTERA 功能描述:NEW |
| EPM7128EQI100-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128LC84-12 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 128-CELL, 12NS PROP DELAY, 84 Pin, Plastic, PLCC |
| EPM7128LC84-15 | 制造商:Altera Corporation 功能描述:COMPLEX-EEPLD, 128-CELL, 15NS PROP DELAY, 84 Pin, Plastic, PLCC |
| EPM7128QC1004 | 制造商:ALTERA 功能描述:* |
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