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Altera Corporation
1
MAX 7000B
Programmable Logic
Device Family
February 2000, ver. 2.0
Data Sheet
A-DS-MAX7000B-01.1
Features...
I
High-performance 2.5-V CMOS EEPROM-based programmable
logic devices (PLDs) built on second-generation Multiple Array
MatriX (MAX
) architecture (see
Table 1
)
–
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
–
High-density PLDs ranging from 600 to 10,000 usable gates
–
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 285.7 MHz
Advanced 2.5-V in-system programmability (ISP)
–
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
–
Enhanced ISP algorithm for faster programming
–
ISP_Done bit to ensure complete programming
–
Pull-up resistor on I/O pins during in-system programming
Preliminary
Information
I
f
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
MAX 7000A devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000A Programmable Logic Device Family Data Sheet
.
Note:
(1)
Contact Altera for up-to-date information on timing information.
Table 1. MAX 7000B Device Features
Note (1)
Feature
EPM7032B
EPM7064B
EPM7128B
EPM7256B
EPM7512B
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
600
32
2
36
1,250
64
4
68
2,500
128
8
100
5,000
256
16
164
10,000
512
32
212
3.5
2.8
1.0
1.9
285.7
3.5
2.7
1.0
2.0
277.8
4.5
3.5
1.0
2.5
212.8
5.0
3.8
1.0
2.9
188.7
6.0
4.3
2.0
3.9
147.1