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参数资料
| 型号： | EPM7256B |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(MAX7000B可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（MAX7000B可编程逻辑系列器件） |
| 文件页数： | 16/125页 |
| 文件大小： | 1053K |
| 代理商： | EPM7256B |
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16
Altera Corporation
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Programming
with External
Hardware
MAX 7000B devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
f
For more information, see the
Altera Programming Hardware Data Sheet
.
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/ O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see
Programming Hardware Manufacturers
.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000B devices include the JTAG boundary-scan test circuitry
defined by IEEE Std. 1149.1.
Table 4
describes the JTAG instructions
supported by MAX 7000B devices. The pin-out tables starting on
page 54
of this data sheet show the location of the JTAG control pins for each
device. If the JTAG interface is not required, the JTAG pins are available
as user I/ O pins.
Table 4. MAX 7000B JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the
boundary-scan test data to pass synchronously through a selected device to adjacent
devices during normal operation.
Allows the values in the boundary-scan register to determine pin states while placing the
1-bit bypass register between the
TDI
and
TDO
pins.
Selects the IDCODE register and places it between the
TDI
and
TDO
pins, allowing the
IDCODE to be serially shifted out of
TDO
.
Selects the 32-bit USERCODE register and places it between the
TDI
and
TDO
pins,
allowing the USERCODE value to be shifted out of
TDO
.
These instructions are used when programming MAX 7000B devices via the JTAG ports
with the MasterBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam
File (
.jam
), Jam Byte-Code File (
.jbc
), or Serial Vector Format File (
.svf
) via an
embedded processor or test equipment.
EXTEST
BYPASS
CLAMP
IDCODE
USERCODE
ISP Instructions
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7256BBC169-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPM7256BBC169-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPM7256BBC169-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPM7256BBI169-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPM7256BBI169-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
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