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Altera Corporation
3
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
–
Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized
modules (LPMs), Verilog HDL, VHDL, and other interfaces to
popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit
(MPU), MasterBlaster
TM
serial/ universal serial bus (USB)
communications cable, and ByteBlasterMV
TM
parallel port
download cable, as well as programming hardware from third-
party manufacturers and any Jam
TM
STAPL File (
.jam
), Jam Byte-
Code File (
.jbc
), or Serial Vector Format File (
.svf
)-capable in-
circuit tester
–
General
Description
MAX 7000B devices are high-density, high-performance devices based on
Altera’s second-generation MAX architecture. Fabricated with advanced
CMOS technology, the EEPROM-based MAX 7000B devices operate with
a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP,
pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 285.7 MHz.
All MAX 7000B device speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG)
PCI Local Bus
Specification, Revision 2.2
. See
Table 2
.
Notes:
(1)
Contact Altera Marketing for up-to-date information on available device speed
grades.
Timing parameters are preliminary.
(2)
Table 2. MAX 7000B Speed Grades
Notes (1)
,
(2)
Device
Speed Grade
-3
v
v
-4
-5
v
v
-6
-7
v
v
v
v
v
-10
EPM7032B
EPM7064B
EPM7128B
v
v
v
v
EPM7256B
v
EPM7512B
v