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| 型号： | EPM9560RC208-15 |
| 文件页数： | 4/42页 |
| 文件大小： | 489K |
| 代理商： | EPM9560RC208-15 |
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12
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler automatically allocates as many as three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2
× t
PEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocells and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance. Figure 6 shows the interconnection of four adjacent LABs
with row and column interconnects.
相关PDF资料 |
PDF描述 |
|---|---|
| EPM9560RC208-20 | |
| EPM9560RC240-15 | |
| EPM9560RC240-20 | |
| EPM9560RC304-15 | |
| EPM9560RI208-15 | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM9560RC208-20 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM9560RC240-15 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM9560RC240-15YY | 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP |
| EPM9560RC240-20 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM9560RC304-15 | 制造商:Altera Corporation 功能描述:IC MAX |
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