参数资料
型号: EV-ADF4360-4EB1Z
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: BOARD EVAL FOR ADF4360-4
标准包装: 1
主要目的: 计时,频率合成器
嵌入式:
已用 IC / 零件: ADF4360-4
主要属性: 带 VCO 的单路整数-N PLL
次要属性: 1.6GHz,200kHz PFD
已供物品: 板,缆线,CD
其它名称: Q7037782
ADF4360-4
Data Sheet
Rev. B | Page 16 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-4 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-4 during initial power-up to have settled.
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not be able to oscillate at the desired frequency,
which does not allow the band select logic to choose the correct
frequency band, and the ADF4360-4 may not achieve lock. If
the recommended interval is inserted, and the N counter latch
is programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-4 VCO. The recom-
mended value of this capacitor is 10 F. Using this value
requires an interval of ≥ 5 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, this capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is ex-
plained further in Table 10.
Table 10. CN Capacitance vs. Interval and Phase Noise
CN Value
Recommended Interval between Control Latch and N Counter Latch
Open-Loop Phase Noise @ 10 kHz Offset
10 F
≥ 5 ms
87 dBc
440 nF
≥ 600 s
86 dBc
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04438-020
Figure 16. ADF4360-4 Power-Up Timing
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