参数资料
型号: EV-ADF4360-4EB1Z
厂商: Analog Devices Inc
文件页数: 9/24页
文件大小: 0K
描述: BOARD EVAL FOR ADF4360-4
标准包装: 1
主要目的: 计时,频率合成器
嵌入式:
已用 IC / 零件: ADF4360-4
主要属性: 带 VCO 的单路整数-N PLL
次要属性: 1.6GHz,200kHz PFD
已供物品: 板,缆线,CD
其它名称: Q7037782
Data Sheet
ADF4360-4
Rev. B | Page 17 of 24
Hardware Power-Up/Power-Down
If the ADF4360-4 is powered down via the hardware (using the
CE pin) and powered up again without any change to the N
counter register during power-down, the part locks at the cor-
rect frequency because it is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <5 ms for 10 F capacitance. The smaller ca-
pacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down because it may not lock to the correct frequency
on power-up. If it is updated, the correct programming se-
quence for the parts after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the ADF4360-4 is powered down via the software (using the
control latch) and powered up again without any change to the
N counter latch during power-down, the part locks at the cor-
rect frequency because it is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <5 ms for 10 F capacitance. The smaller ca-
pacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down because it may not lock to the correct frequency
on power-up. If it is updated, the correct programming se-
quence for the part after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
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