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| 型号： | EVAL-AD5379EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5379 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| DAC 的数量： | 40 |
| 位数： | 14 |
| 采样率（每秒）： | 50k |
| 数据接口： | 串行，并联 |
| 设置时间： | 20µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5379 |
| 相关产品： | AD5379ABCZ-ND - IC DAC 14BIT 40CHAN 108CSPBGA AD5379ABC-ND - IC DAC 14BIT 40CH 108-CSPBGA |
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AD5379
Rev. B | Page 18 of 28
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5379 contains 40 DAC channels and 40 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 14-bit resistor-string DAC followed by an
output buffer amplifier. The resistor-string section is simply a
string of resistors, each of value R, from VREF(+) to AGND. This
type of architecture guarantees DAC monotonicity. The 14-bit
binary digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off before being
fed into the output amplifier. The output amplifier translates the
output of the DAC to a wider range. The DAC output is gained
up by a factor of 3.5 and offset by the voltage on the VREF() pin.
See the Transfer Function section for more information.
CHANNEL GROUPS
The 40 DAC channels on the AD5379 are arranged into four
groups (A, B, C, D) of 10 channels. In each group, eight
channels are connected to VREF1(+) and VREF1(), and the
remaining two channels are connected to VREF2(+) and
VREF2(). Each group has two individual REFGND pins. For
example, in Group A, eight channels are connected to
REFGNDA1, and the remaining two channels are connected to
REFGNDA2. In addition to an input register (x1) and a DAC
register (x2), each channel has a gain register (m) and an offset
register (c). See Table 17. The inclusion of these registers allows
the user to calibrate out errors in the complete signal chain,
including the DAC errors.
Table 9 shows the reference and REFGND inputs, and the
m and c registers for Group A. Groups B, C, and D are similar.
Table 9. Inputs and Registers for Group A
Channel
Reference
REFGND
m, c Registers
0 to 7
VREF1(+), VREF1()
REFGNDA1
m REG0 to REG7
c REG0 to REG7
8 and 9
VREF2(+), VREF2()
REFGNDA2
m REG8 and REG9
c REG8 and REG9
TRANSFER FUNCTION
The digital input transfer function for each DAC can be
represented as
x2 = [(m + 1)/213 × x1] + (c 2n1)
where:
x2 is the data-word loaded to the resistor string DAC.
(Default is 10 0000 0000 0000.)
x1 is the 14-bit data-word written to the DAC input register.
(Default is 10 0000 0000 0000.)
m is the 13-bit gain coefficient. (Default is 1 1111 1111 1111.)
c is the 14-bit offset coefficient. (Default is 10 0000 0000 0000.)
n is the DAC resolution (n = 14).
Figure 19 shows a single DAC channel and its associated
registers. The power-on values for the m and c registers are full
scale and 0x2000, respectively. The user can individually adjust
the voltage range on each DAC channel by overwriting the
power-on values of m and c. The AD5379 has digital overflow
and underflow detection circuitry to clamp the DAC output at
full scale or zero scale when the values chosen for x1, m, and c
result in x2 being out of range.
DAC
x2
VREF(+)
AGND
x2
REG
x1 INPUT
REG
DAC
m REG
c REG
INPUT
DATA
VDAC
DAC
REG
LDAC
03165-019
Figure 19. Single DAC Channel
The complete transfer function for the AD5379 can be
represented as
VOUT = 3.5 × ((VREF(+) AGND) × x2/214) +
2.5 × (VREF() AGND) + REFGND
where:
x2 is the data word loaded to the resistor string DAC.
VREF(+) is the voltage at the positive reference pin.
VREF() is the voltage at the negative reference pin.
Figure 20 shows the output amplifier stage of a single channel.
VDAC is the voltage output from the resistor string DAC. The
nominal range of VDAC is 1 LSB to full scale.
VDAC
R
2.5R
VOUT
VREF(–)
REFGND
AGND
03165-020
Figure 20. Output Amplifier Stage
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