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| 型号： | EVAL-AD5379EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5379 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| DAC 的数量： | 40 |
| 位数： | 14 |
| 采样率（每秒）： | 50k |
| 数据接口： | 串行，并联 |
| 设置时间： | 20µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5379 |
| 相关产品： | AD5379ABCZ-ND - IC DAC 14BIT 40CHAN 108CSPBGA AD5379ABC-ND - IC DAC 14BIT 40CH 108-CSPBGA |
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AD5379
Rev. B | Page 6 of 28
TIMING CHARACTERISTICS
SERIAL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = 11.4 V to 16.5 V; VREF(+) = 5 V; VREF() = 3.5 V; AGND = DGND = REFGND = 0 V;
VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Unit
Description
t1
20
ns min
SCLK cycle time.
t2
8
ns min
SCLK high time.
t3
8
ns min
SCLK low time.
t4
10
ns min
SYNC falling edge to SCLK falling edge setup time.
15
ns min
24th SCLK falling edge to SYNC falling edge.
25
ns min
Minimum SYNC low time.
t7
10
ns min
Minimum SYNC high time.
t8
5
ns min
Data setup time.
t9
4.5
ns min
Data hold time.
30
ns max
24th SCLK falling edge to BUSY falling edge.
t11
330
ns max
BUSY pulse width low (single-channel update). See
.
t124
20
ns min
24th SCLK falling edge to LDAC falling edge.
t13
20
ns min
LDAC pulse width low.
t14
150
ns typ
BUSY rising edge to DAC output response time.
t15
0
ns min
BUSY rising edge to LDAC falling edge.
t16
100
ns min
LDAC falling edge to DAC output response time.
t17
20/30
μs typ/max
DAC output settling time.
t18
10
ns min
CLR pulse width low.
t19
350
ns max
CLR/RESET pulse activation time.
25
ns max
SCLK rising edge to sdo valid.
t217
5
ns min
SCLK falling edge to SYNC rising edge.
t227
5
ns min
SYNC rising edge to SCLK rising edge.
t237
20
ns min
SYNC rising edge to LDAC falling edge.
t245
30
ns min
SYNC rising edge to BUSY falling edge.
t25
10
ns min
RESET pulse width low.
t26
120
μs max
RESET time indicated by BUSY low.
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 Standalone mode only.
5 This is measured with the load circuit shown in Figure 2.
6 This is measured with the load circuit shown in Figure 3.
7 Daisy-chain mode only.
TO
OUTPUT
PIN
VCC
VOL
CL
50pF
RL
2.2k
Ω
03165-002
Figure 2. Load Circuit for BUSY Timing Diagram
2
VOH(min) + VOL(max)
200
μA
200
μA
IOL
IOH
CL
50pF
TO
OUTPUT
PIN
03165-003
Figure 3. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
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