参数资料
型号: EVAL-AD5382EBZ
厂商: Analog Devices Inc
文件页数: 25/40页
文件大小: 0K
描述: BOARD EVAL FOR AD5382
产品培训模块: DAC Architectures
标准包装: 1
DAC 的数量: 32
位数: 14
采样率(每秒): 125k
数据接口: DSP,I²C,MICROWIRE?,并行,QSPI?,SPI?
设置时间: 8µs
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5382
其它名称: Q4391457
Data Sheet
AD5382
Rev. C | Page 31 of 40
MICROPROCESSOR INTERFACING
Parallel Interface
The AD5382 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 34 shows the AD5382 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0–A4 on the AD5382. The upper address lines are decoded
to provide a CS, LDAC signal for the AD5382. The fast interface
timing of the AD5382 allows direct interface to a wide variety
of microcontrollers and DSPs, as shown in Figure 34.
AD5382 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the
SCLK of the AD5382, the MOSI output drives the serial data
line (DIN) of the AD5382, and the MISO input is driven from
DOUT. The SYNC signal is derived from a port line (PC7).
When data is being transmitted to the AD5382, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
03733-034
MC68HC111
AD53821
MISO
MOSI
SCK
PC7
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5382-to-MC68HC11 Interface
03733-035
CONTROLLER/
DSP PROCESSOR1
AD53821
ADDRESS
DECODE
UPPER BITS OF
ADDRESS BUS
DATA
BUS
D15
D0
A4
A3
A2
A1
A0
R/W
A4
A3
A2
A1
A0
WR
REG1
REG0
D13
D0
CS
LDAC
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 34. AD5382-to-Parallel Interface
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