参数资料
型号: EVAL-AD5382EBZ
厂商: Analog Devices Inc
文件页数: 3/40页
文件大小: 0K
描述: BOARD EVAL FOR AD5382
产品培训模块: DAC Architectures
标准包装: 1
DAC 的数量: 32
位数: 14
采样率(每秒): 125k
数据接口: DSP,I²C,MICROWIRE?,并行,QSPI?,SPI?
设置时间: 8µs
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5382
其它名称: Q4391457
Data Sheet
AD5382
Rev. C | Page 11 of 40
PARALLEL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications Tmin to Tmax,
unless otherwise noted.
Table 7.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t0
4.5
ns min
REG0, REG1, address to WR rising edge setup time
t1
4.5
ns min
REG0, REG1, address to WR rising edge hold time
t2
20
ns min
CS pulse width low
t3
20
ns min
WR pulse width low
t4
0
ns min
CS to WR falling edge setup time
t5
0
ns min
WR to CS rising edge hold time
t6
4.5
ns min
Data to WR rising edge setup time
t7
4.5
ns min
Data to WR rising edge hold time
t8
20
ns min
WR pulse width high
t94
700
ns min
Minimum WR cycle time (single-channel write)
30
ns max
WR rising edge to BUSY falling edge
670
ns max
BUSY pulse width low (single-channel update)
t12
30
ns min
WR rising edge to LDAC falling edge
t13
20
ns min
LDAC pulse width low
t14
100
ns max
BUSY rising edge to DAC output response time
t15
20
ns min
LDAC rising edge to WR rising edge
t16
0
ns min
BUSY rising edge to LDAC falling edge
t17
100
ns min
LDAC falling edge to DAC output response time
t18
2
s typ
DAC output settling time
t19
20
ns min
CLR pulse width low
t20
35
smax
CLR pulse activation time
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3
4
5
Measured with the load circuit of Figure 2.
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