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| 型号： | EVAL-AD5520EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5520 |
| 标准包装： | 1 |
| 主要目的： | 测试与测量，每引脚参数测量单元（PPMU） |
| 已用 IC / 零件： | AD5520 |
| 已供物品： | 板 |
| 相关产品： | AD5520JSTZ-ND - IC PPMU SNGL-CH 64-LQFP |
AD5520
Rev. B | Page 16 of 24
CIRCUIT OPERATION
FORCE VOLTAGE
Most PMU measurements are performed while in force voltage
and measure current modes; for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage at analog input
FIN is mapped directly to the voltage forced at the DUT.
When in force voltage and measure current modes, the
maximum voltage applied to the input corresponds to the
maximum current outputs. Figure 22 shows the transfer
function when forcing a voltage.
VDUT
VCLL ×
RS × 16
RDUT
VCLH ×
RS × 16
RDUT
RS × 16
VCLH
RS × 16
VCLL
VCLH
IDUT
VFIN
03701-022
Figure 22. Force Voltage Transfer Function
MEASURE CURRENT
Figure 23 shows a simplified diagram of the PMU when in force
voltage mode. The control loop consists of the force amplifier
with the voltage sense amplifier making up the feedback path.
Current flowing through the DUT is measured by sensing the
current flowing through a selectable sense resistor, which is in
series with the DUT. The current sense amplifier (Gain = 16)
generates a voltage at its output, which is proportional to the
current flowing through the DUT. This voltage is compared to
the CLL and CLH levels to ensure the clamp voltages have not
been exceeded. Strobing CPCK and STB provides information
about the voltage level with respect to the comparator levels,
CPH and CPL.
MEASIHx
MEASIL
G= 16
MEASVH
MEASVL
G = 1
FOHx
RS
RDUT
FIN
VMEASIOUT
VMEASVOUT
MEASI
O
UT
MEASVOUT
CLH
CLL
VCLL
VCLH
VFIN
CONDITION
OUTPUT
VCLH > IDUT × RS × 16
VCLL < IDUT × RS × 16
VDUT = VFIN
VDUT = VCLH
VDUT = VCLL
VCLH > IDUT × RS × 16
VCLL > IDUT × RS × 16
VCLH < IDUT × RS × 16
VCLL < IDUT × RS × 16
REFGNDI/V
V
03701-
023
Figure 23. Force Voltage, Measure Current Mode
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