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| 型号： | EVAL-AD5590EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5590 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 输入范围： | 2 Vpp |
| 在以下条件下的电源（标准）： | 12.5mW @ 1MSPS，5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD5590 |
| 已供物品： | 板 |
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AD5590
Rev. A | Page 30 of 44
SERIAL INTERFACE
The AD5590 contains independent serial interfaces for the
ADC and DAC sections. The ADC uses the ASYNC, ASCLK,
ADIN, and ADOUT pins. The VDRIVE pin allows the user to
determine the output voltage of logic high signals. The DAC
uses DSCLK, DDIN, DSYNC1, DSYNC2, LDAC, and CLR.
The 16 analog input channels use the ADC interface. The 16
output channels use the DAC interface. The 16 output channels
are divided into two groups of eight channels, which can be
controlled independently. Each group has its own set of control
registers. When addressing the DAC control registers, the serial
data should be framed by DSYNC1 to access the control registers
for DAC0 to DAC7 and framed by DSYNC2 to access the control
registers for DAC8 to DAC15.
The interfaces are compatible with SPI, QSPI, MICROWIRE,
and most DSPs.
ACCESSING THE DAC BLOCK
Figure 4 shows a timing diagram of a typical write sequence to
the DAC block. The write sequence begins by bringing one or
both of the DSYNC lines low. If DSYNC1 is brought low, the
data is written to the DAC block containing DAC0 to DAC7.
If DSYNC2 is brought low, the data is written to the DAC block
containing DAC8 to DAC15. If both DSYNC1 and DSYNC2 are
brought low, the data is written into both blocks simultaneously.
Figure 60 shows how the serial interface is arranged.
DDIN
DSYNC1
DSCLK
CLR
LDAC
GROUP 1
CONTROL
REGISTERS
DSYNC2
VOUT0
DAC 0
VOUT7
DAC 7
GROUP 2
CONTROL
REGISTERS
VOUT8
DAC 8
VOUT15
DAC 15
07691-
060
Figure 60. DAC Serial Interface Configuration
Data from the DDIN line is clocked into the 32-bit shift register
on the falling edge of DSCLK. The serial clock frequency can be
as high as 50 MHz, making the AD5590 compatible with high
speed DSPs. On the 32nd falling clock edge, the last data bit is
clocked in and the programmed function is executed, that is,
a change in DAC register contents and/or a change in the mode
of operation. At this stage, the DSYNCx line can be kept low
or be brought high. In either case, it must be brought high for
a minimum of 15 ns before the next write sequence so that a
falling edge of DSYNCx can initiate the next write sequence.
DAC Input Shift Register
The input shift register is 32 bits wide (see Figure 61). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 11), followed by the 4-bit DAC address,
A3 to A0 (see Table 12), and finally the 12-bit data-word. The
data-word comprises the 12-bit input code followed by eight
don’t care bits. These data bits are transferred to the DAC
register on the 32nd falling edge of DSCLK.
Table 11. DAC Command Definitions
Command
C3
C2
C1
C0
Description
0
Write to Input Register n
0
1
Update DAC Register n
0
1
0
Write to Input Register n, update all
(Software LDAC)
0
1
Write to and update DAC Channel n
0
1
0
Power down/power up DAC
0
1
0
1
Load clear code register
0
1
0
Load LDAC register
0
1
Reset (power-on reset)
1
0
Set up internal REF register
1
0
1
Reserved
…
Reserved
1
Reserved
Table 12. DAC Address Commands
Address (n)
Selected DAC Channel
A3
A2
A1
A0
DSYNC1 Low
DSYNC2 Low
0
DAC0
DAC8
0
1
DAC1
DAC9
0
1
0
DAC2
DAC10
0
1
DAC3
DAC11
0
1
0
DAC4
DAC12
0
1
0
1
DAC5
DAC13
0
1
0
DAC6
DAC14
0
1
DAC7
DAC15
1
DAC0 to DAC7
DAC8 to DAC15
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
07691-
061
Figure 61. DAC Input Register Contents
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