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| 型号： | EVAL-AD5590EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5590 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 输入范围： | 2 Vpp |
| 在以下条件下的电源（标准）： | 12.5mW @ 1MSPS，5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD5590 |
| 已供物品： | 板 |
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AD5590
Rev. A | Page 13 of 44
Pin No.
Mnemonic
Description
L7
ASCLK
Serial Clock. Logic input. ASCLK provides the serial clock for accessing data from the ADC block. This
clock input is also used as the clock source for the conversion process of the ADC.
L6
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial
interface of the ADC block operates.
A4, B8
DACVDD
Power Supply Input for the DAC Block. The DAC can operate from 4.5 V to 5.25 V, and the supply
should be decoupled with a 10 F in parallel with a 0.1 F capacitor to DACGND. The two DACVDD pins
must be connected together.
A9, B5
DACGND
Ground Reference Point for the DAC Block. All DAC analog/digital input/output signals and any
external reference signal should be referred to this DACGND voltage. The two DACGND pins should be
connected together.
A8
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently
low.
A5
DSYNC1
Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels
VOUT0 to VOUT7. When DSYNC1 goes low, it powers on the DSCLK and DDIN buffers and enables the
input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC1 is taken
high before the 32nd falling edge, the rising edge of DSYNC1 acts as an interrupt and the write
sequence is ignored by the device.
B7
DSYNC2
Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels
VOUT8 to VOUT15. When DSYNC2 goes low, it powers on the DSCLK and DDIN buffers and enables the
input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC2 is taken
high before the 32nd falling edge, the rising edge of DSYNC2 acts as an interrupt and the write
sequence is ignored by the device.
B6
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero scale, midscale, or full scale. Default setting clears the output
to 0 V.
A7
DDIN
DAC Data Input. This DAC has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
A6
DSCLK
DAC Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
A1, B9, C2, B4, D2,
A3, E2, A2
VOUT0 to
VOUT7
Analog Output Voltage from DAC0 to DAC7. DSYNC1 is the frame synchronization signal for writing
data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if
it is high. The output amplifiers have rail-to-rail operation.
A10, C11, A11, D11,
B10, E11, A12, F11
VOUT8 to
VOUT15
Analog Output Voltage from DAC8 to DAC15. DSYNC2 is the frame synchronization signal for writing
data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if
it is high. The output amplifiers have rail to rail operation.
F2
VREFIN1/
VREFOUT1
Reference Input/Output Pin for DAC0 to DAC7. The DACs have a common pin for reference input and
reference output. When using the internal reference, this is the reference output pin. When using an
external reference, this is the reference input pin. The default for this pin is as a reference input.
G11
VREFIN2/
VREFOUT2
Reference Input/Output Pin for DAC8 to DAC15. The DACs have a common pin for reference input and
reference output. When using the internal reference, this is the reference output pin. When using an
external reference, this is the reference input pin. The default for this pin is as a reference input.
M3
V1+
Positive Supply Input for the amplifier 0 to amplifier 3. The supply for these amplifiers is independent
of other supplies and can be operated with a different supply if required. The pin should be decoupled
to V1 with a 10 F in parallel with a 0.1 F capacitor.
H2
V1
Negative Supply Input for Amplifier 0 to Amplifier 3.
L9
V2+
Positive Supply Input for Amplifier 4 to Amplifier 7. The supply for these amplifiers is independent of
other supplies and can be operated with a different supply if required. The pin should be decoupled
to V2 with a 10 F in parallel with a 0.1 F capacitor.
H12
V2
Negative Supply Input for Amplifier 4 to Amplifier 7.
M1, J1, D1, F1, M10,
L12, G12, D12
IN0() to
IN7()
Inverting Input Terminals for Operational Amplifier 0 to Amplifier 7.
M2, K1, C1, E1, M11,
M12, F12, E12
IN0(+) to
IN7(+)
Noninverting Input Terminals for Operational Amplifier 0 to Amplifier 7.
L1, H1, B1, G1, M9,
K12, J12, C12
OUT0 to
OUT7
Output Terminals for Operational Amplifier 0 to Amplifier 7.
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