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参数资料
| 型号： | EVAL-AD7674CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7674 |
| 产品培训模块： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 18 |
| 采样率（每秒）： | 800k |
| 数据接口： | 串行，并联 |
| 输入范围： | 0 ~ 5 V |
| 在以下条件下的电源（标准）： | 126mW @ 800kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7674 |
| 已供物品： | 板 |
| 相关产品： | AD7674ACPZ-ND - IC ADC 18BIT SAR 5V 48LFCSP AD7674ACPZRL-ND - IC ADC 18BIT SAR 5V 48LFCSP AD7674ASTZ-ND - IC ADC 18BIT 800KSPS 48-LQFP AD7674ASTZRL-ND - IC ADC 18BIT 800KSPS 48-LQFP T/R |
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AD7674
Rev. A | Page 23 of 28
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7674 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
Though maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on the rising and falling edge of the clock.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Also, data can be read at speeds up to 40 MHz, accommodating
both slow digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7674 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 44. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
SCLK
SDOUT
D17
D16
D1
D0
D15
X17
X16
X15
X1
X0
Y17
Y16
BUSY
SDIN
INVSCLK = 0
X17
X16
X
12
3
16
17
18
19
20
EXT/INT = 1
RD = 0
t35
t36 t37
t31
t32
t34
t16
t33
CS
03083-0-042
Figure 42. Slave Serial Data Timing for Reading (Read after Convert)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD7674EDZ | 功能描述:BOARD EVAL FOR AD7674 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7675CB | 制造商:AD 制造商全称:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
| EVAL-AD7675CBZ | 功能描述:BOARD EVALUATION FOR AD7675 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:PulSAR® 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7676CB | 制造商:AD 制造商全称:Analog Devices 功能描述:Evaluation Board AD766X/AD767X |
| EVAL-AD7676CBZ | 功能描述:BOARD EVALUATION FOR AD7676 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:PulSAR® 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
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