参数资料
型号: EVAL-AD7676CBZ
厂商: Analog Devices Inc
文件页数: 6/20页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7676
标准包装: 1
系列: PulSAR®
ADC 的数量: 1
位数: 16
采样率(每秒): 500k
数据接口: 串行,并联
输入范围: ±VREF
在以下条件下的电源(标准): 67mW @ 500kSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7676
已供物品:
相关产品: AD7676ASTZRL-ND - IC ADC 16BIT DIFF INP 48LQFP
AD7676ASTZ-ND - IC ADC 16BIT 500KSPS DIFF 48LQFP
REV. B
AD7676
–14–
t9
RESET
DATABUS
BUSY
CNVST
t8
Figure 12. RESET Timing
For other applications, conversions can be automatically initiated.
If
CNVST is held LOW when BUSY is LOW, the AD7676
controls the acquisition phase and then automatically initiates a
new conversion. By keeping
CNVST LOW, the AD7676 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up,
CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7676 could sometimes
run slightly faster than the guaranteed limit of 500 kSPS.
DIGITAL INTERFACE
The AD7676 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel databus. The
AD7676 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7676
to the host system interface digital supply. Finally, by using the
OB/
2C input pin, either twos complement or straight binary
coding can be used.
The two signals
CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually,
CS allows the selection of each AD7676 in
multicircuit applications and is held LOW in a single AD7676
design.
RD is generally used to enable the conversion result on
the databus.
CNVST
BUSY
DATABUS
CS = RD = 0
PREVIOUS CONVERSION DATA
NEW DATA
t1
t10
t4
t3
t11
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7676 is configured to use the parallel interface (Figure 13)
when the SER/
PAR is held LOW. The data can be read either
after each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the first
half of the conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
DATABUS
t12
t13
BUSY
CS
RD
CURRENT
CONVERSION
Figure 14. Slave Parallel Data Timing for Reading
(Read after Conversion)
CS = 0
CNVST,
RD
t1
PREVIOUS
CONVERSION
DATABUS
t12
t13
BUSY
t4
t3
Figure 15. Slave Parallel Data Timing for Reading (Read
during Conversion)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t12
t13
Figure 16. 8-Bit Parallel Interface
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