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| 型号： | EVAL-AD7685SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7685 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 10mW @ 250kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7685 |
| 已供物品： | 板 |
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AD7685
Rev. C | Page 16 of 28
DRIVER AMPLIFIER CHOICE
Although the AD7685 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7685. Note that the AD7685 has a
noise much lower than most of the other 16-bit ADCs and,
therefore, can be driven by a noisier amplifier to meet a given
system noise specification. The noise coming from the
amplifier is filtered by the AD7685 analog input circuit low-
pass filter made by RIN and CIN or by an external filter, if one
is used. Because the typical noise of the AD7685 is 35 μV
rms, the SNR degradation due to the amplifier is
+
=
2
3dB
2
)
(
f
2
π
35
20log
N
LOSS
Ne
SNR
where:
f–3dB is the input bandwidth in MHz of the AD7685
(2 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
For ac applications, the driver should have a THD
performance commensurate with the AD7685. Figure 17
shows the AD7685’s THD vs. frequency.
For multichannel, multiplexed applications, the driver
amplifier and the AD7685 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 16-bit level and
should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier
Typical Application
Very low noise and low power
5 V single-supply, low power
5 V single-supply, low power
Low power, low noise, and low frequency
Very low noise and high frequency
Very low noise and high frequency
Small, low power and low frequency
High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7685 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7685 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a 16-bit resolution system with low
supply and respectable performance. It uses two power supply
pins: a core supply VDD and a digital input/output interface
supply VIO. VIO allows direct interface with any logic between
1.8 V and VDD. To reduce the number of supplies needed, the
VIO and VDD can be tied together. The AD7685 is independent of
power supply sequencing between VIO and VDD. Additionally,
it is very insensitive to power supply variations over a wide
frequency range, as shown in Figure 31, which represents PSRR
over frequency.
02
96
8-
0
29
FREQUENCY (kHz)
10000
1
10
100
1000
P
S
RR
(
d
B)
110
80
90
100
70
60
50
40
30
VDD = 5V
VDD = 2.5V
Figure 31. PSRR vs. Frequency
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