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参数资料
| 型号： | EVAL-AD7687SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7687 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 4mW @ 5V，100kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7687 |
| 已供物品： | 板 |
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Data Sheet
AD7687
Rev. B | Page 23 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7687s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7687s is shown
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
Figure 45) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7687 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7687s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to eight AD7687s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
02972-
044
CNV
SCK
SDO
SDI
AD7687
C
CNV
SCK
SDO
SDI
AD7687
A
CNV
SCK
SDO
SDI
AD7687
B
Figure 45. Chain Mode with BUSY Indicator Connection Diagram
SDOA = SDIB
DA15 DA14 DA13
SCK
123
35
47
48
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
415
tSCK
tSCKH
tSCKL
DA0
17
34
16
SDOB = SDIC
DB15 DB14 DB13
DA1
DB1DB0DA15 DA14
49
tSSDISCK
tHSDISC
tHSDO
tDSDO
SDOC
DC15 DC14 DC13
DA1DA0
DC1DC0DA14
19
31
32
18
33
DB1DB0DA15
DB15 DB14
tDSDOSDI
tSSCKCNV
tHSCKCNV
02972-045
DA0
tDSDOSDI
Figure 46. Chain Mode with BUSY Indicator Serial Interface Timing
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