- 您现在的位置：买卖IC网 > PDF目录17060 > EVAL-AD7766-2EDZ (Analog Devices Inc)BOARD EVAL AD7766-2 32KSPS 114DB PDF资料下载
参数资料
| 型号： | EVAL-AD7766-2EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/25页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7766-2 32KSPS 114DB |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 32k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 8.5mW @ 32kSPS |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7766-2 |
| 已供物品： | 板，CD |
| 相关产品： | AD7766BRUZ-2-ND - IC ADC 24BIT 32KSPS SAR 16TSSOP AD7766BRUZ-1-ND - IC ADC 24BIT 64KSPS SAR 16TSSOP AD7766BRUZ-ND - IC ADC 24BIT 128KSPS SAR 16TSSOP AD7766BRUZ-RL7-ND - IC ADC 24BIT 128KSPS SAR 16TSSOP AD7766BRUZ-2-RL7-ND - IC ADC 24BIT 32KSPS SAR 16TSSOP AD7766BRUZ-1-RL7-ND - IC ADC 24BIT 64KSPS SAR 16TSSOP |
AD7766
Rev. C | Page 18 of 24
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple ADCs
on a single data line. This feature is especially useful for reduc-
ing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register where data is clocked on the falling edge of SCLK.
The block diagram in Figure 36 shows how devices must be
connected to achieve daisy-chain functionality. The scheme
shown operates by passing the output data of the SDO pin of an
AD7766 device to the SDI input of the next AD7766 device in
the chain. The data then continues through the chain until it is
clocked onto the SDO pin of the first device in the chain.
READING DATA IN DAISY-CHAIN MODE
An example of a daisy chain of four AD7766 devices is shown in
output of the AD7766 labeled A is the output of the full daisy
chain. The last device in the chain (the AD7766 labeled D) has
its serial data input (SDI) pin connected to ground. All the
devices in the chain must use common MCLK, SCLK, CS, and
SYNC/PD signals.
To enable the daisy-chain conversion process, apply a common
SYNC/PD pulse to all devices, synchronizing all the devices in
the chain (see the
section).
After applying a SYNC/PD pulse to all the devices, there is a
delay (as listed in
) before valid conversion data appears
at the output of the chain of devices. As shown in
, the
first conversion result is output from the AD7766 device labeled
A. This 24-bit conversion result is followed by the conversion
results from the devices labeled B, C, and D, with all conversion
results output in an MSB-first sequence. The stream of conversion
results is clocked through each device in the chain and is eventually
clocked onto the SDO pin of the AD7766 device labeled A. The
conversion results of all the devices in the chain must be clocked
onto the SDO pin of the final device in the chain while its
DRDY
signal is active low. This is illustrated in the examples shown
(
and
), where the conversion results from
the devices labeled A, B, C, and D are clocked onto SDO (A)
during the time between the falling edge of
DRDY (A) and the
rising edge of DRDY (A).
CHOOSING THE SCLK FREQUENCY
As shown in Figure 37, the number of SCLK falling edges that
occurs during the period when DRDY (A) is active low must
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).
The period of SCLK (tSCLK) required for a known daisy-chain length
using a known common MCLK frequency must, therefore, be
established in advance. Note that the maximum SCLK frequency
voltages.
In the case where CS is tied logic low,
×
≤
K
t
READ
SCLK
24
(1)
where:
K
is the number of AD7766/AD7766-1/AD7766-2 devices in
the chain.
tSCLK
is the period of the SCLK.
tREAD
equals tDRDY t5.
In the case where CS is used in the daisy-chain interface,
(
) (
)
×
+
≤
K
t
13
7
6
READ
SCLK
24
(2)
where:
K
is the number of AD7766/AD7766-1/AD7766-2 devices in
the chain.
tSCLK
is the period of the SCLK.
tREAD
equals tDRDY t5.
Note that the maximum value of SCLK is governed by t8 and is
相关PDF资料 |
PDF描述 |
|---|---|
| SLPX153M035E7P3 | CAP ALUM 15000UF 35V 20% SNAP |
| 0210490303 | CABLE JUMPER 1.25MM .076M 24POS |
| MIC2015-0.8YM6 TR | IC DISTRIBUTION SW 0.8A SOT23-6 |
| EVAL-AD7767-2EDZ | BOARD EVALUATION FOR AD7767 |
| VE-B34-EY | CONVERTER MOD DC/DC 48V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD7766EDZ | 功能描述:BOARD EVAL AD7766 128KSPS 108DB RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7767-1EDZ | 功能描述:BOARD EVAL AD7767-1 64KSPS 111DB RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7767-2EDZ | 功能描述:BOARD EVALUATION FOR AD7767 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7767EDZ | 功能描述:BOARD EVAL AD7767 128KSPS 108DB RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7780EBZ | 功能描述:BOARD EVAL FOR AD7780 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
发布紧急采购，3分钟左右您将得到回复。