参数资料
型号: EVAL-AD7946CBZ
厂商: Analog Devices Inc
文件页数: 11/24页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7946
标准包装: 1
系列: PulSAR®
ADC 的数量: 1
位数: 14
采样率(每秒): 500k
数据接口: 串行
输入范围: 0 ~ 5.5 V
在以下条件下的电源(标准): 19mW @ 500kSPS,5 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7946
已供物品: 板,CD
相关产品: AD7946BCPZRL7TR-ND - IC ADC 14BIT 500KSPS 10-LFCSP
AD7946BCPZRL-ND - IC ADC 14BIT 500KSPS 10-LFCSP
AD7946BRMZRL7-ND - IC ADC 14BIT 500KSPS 10-MSOP
AD7946BRMZ-ND - IC ADC 14BIT 500KSPS SAR 10-MSOP
AD7946
Rev. A | Page 19 of 24
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7946s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7946s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7946 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subse-
quent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 14th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7946 can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
04656-036
CNV
SCK
SDO
SDI
AD7946
CNV
SCK
SDO
SDI
AD7946
Figure 37. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO
D13
D12
D11
D1
D0
tDIS
SCK
12
3
26
27
28
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
12
13
tSCK
tSCKL
tSCKH
D0
D13
D12
15
16
14
SDI(CS2)
04656-037
Figure 38. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
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