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参数资料
| 型号： | EVAL-AD7986EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7986 |
| 产品培训模块： | Motor Control |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 18 |
| 采样率（每秒）： | 2M |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 29mW @ 2MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7986 |
| 已供物品： | 板 |
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AD7986
Rev. B | Page 20 of 28
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7986 is connected
to an SPI-compatible digital host having an interrupt input.
It is only available in normal conversion mode (TURBO = low).
The connection diagram is shown in Figure 27, and the
corresponding timing is given in Figure 28.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. SDO
is maintained in high impedance until the completion of the
conversion irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can be used to select other SPI devices,
such as analog multiplexers, but CNV must be returned low
before the minimum conversion time elapses and then held low
for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
reading controlled by the digital host. The AD7986 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 19th SCK falling edge, SDO returns
to high impedance.
If multiple AD7986 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
AD7986
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
IRQ
VIO
47k
TURBO
07956-
020
Figure 27. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDO
D17
D16
D1
D0
tDIS
SCK
1
2
3
17
18
19
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
TURBO = 0
SDI = 1
tCNVH
tACQ
tQUIET
(QUIET
TIME)
07956-
021
Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
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