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| 型号： | EVAL-AD7986EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7986 |
| 产品培训模块： | Motor Control |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 18 |
| 采样率（每秒）： | 2M |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 29mW @ 2MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7986 |
| 已供物品： | 板 |
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AD7986
Rev. B | Page 24 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7986
devices on a 3-wire serial interface while providing a busy
indicator. This feature is useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7986 devices is
shown in Figure 35, and the corresponding timing is given in
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7986 ADC labeled C in Figure 35) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7986 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge can be used to capture the data, a digital
host using the SCK falling edge allows a faster reading rate and
consequently more AD7986 devices in the chain, provided that
the digital host has an acceptable hold time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7986
SDI
SDO
CNV
C
SCK
AD7986
SDI
SDO
CNV
A
SCK
IRQ
AD7986
SDI
SDO
CNV
B
SCK
TURBO
07956-
028
Figure 35. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIB
DA17 DA16 DA15
SCK
1
2
3
39
53
54
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
4
17
tSCK
tSCKH
tSCKL
DA0
19
38
18
SDOB = SDIC
DB17 DB16 DB15
DA1
DB1
DB0 DA17 DA16
55
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC17 DC16 DC15
DA1
DA0
DC1
DC0
DA16
21
35
36
20
37
DB1
DB0 DA17
DB17 DB16
tDSDOSDI
tHSCKCNV
DA0
tDSDOSDI
TURBO = 0
tQUIET
07956-
029
Figure 36. Chain Mode with Busy Indicator Serial Interface Timing
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