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| 型号： | EVAL-AD9838SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9838 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9838 |
| 主要属性： | USB 供电或外部电源 |
| 次要属性： | SPI 接口 |
| 已供物品： | 板，线缆，CD，文档 |
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AD9838
Rev. A | Page 16 of 32
The prominence of the aliased images depends on the ratio of
fOUT to MCLK. If the ratio is small, the aliased images are very
prominent and of a relatively high energy level as determined by
the sin(x)/x roll-off of the quantized DAC output. In fact, depend-
ing on the fOUT/reference clock ratio, the first aliased image can
be on the order of 3 dB below the fundamental.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. To avoid unwanted (and unexpected)
output anomalies, it is necessary to consider the relationship of
the selected output frequency and the reference clock frequency.
To apply the AD9838 as a clock generator, limit the selected
output frequency to <33% of the reference clock frequency. In
this way, the user can prevent the generation of aliased signals
that fall within, or close to, the output band of interest (generally
the dc selected output frequency). This practice reduces the
complexity (and cost) of the external filter requirement for the
clock generator application. For more information, see the
To enable the comparator, the SIGN/PIB and OPBITEN bits in
the control resister must be set to 1 (see Table 18).
REGULATOR
The AD9838 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both supplies can have a value of 2.3 V to
5.5 V and are independent of each other. For example, the
analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
The internal digital section of the AD9838 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9838 also
operates from DVDD. These digital signals are level shifted
within the AD9838 to make them 2.5 V compatible.
If the voltage applied at the DVDD pin of the AD9838 is less than
or equal to 2.7 V, the CAP/2.5V and DVDD pins should be tied
together to bypass the on-board regulator.
SYSTEM CLOCK
fOUT
fC – fOUT
fC + fOUT
2
fC – fOUT
2
fC + fOUT
3
fC – fOUT
3
fC + fOUT
fC
0Hz
FIRST
IMAGE
SECOND
IMAGE
THIRD
IMAGE
FOURTH
IMAGE
FIFTH
IMAGE
SIXTH
IMAGE
2
fC
3
fC
FREQUENCY (Hz)
SI
G
N
A
L
A
M
PL
IT
U
D
E
sin(x)/x ENVELOPE
x = π (
f/fC)
09
07
7
-04
0
Figure 21. DAC Output Spectrum
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