参数资料
| 型号： | EVAL-ADE7880EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 94/104页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADE7880 |
| 标准包装： | 1 |
| 系列： | * |
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ADE7880
Data Sheet
Bit
20
Mnemonic
MISMTCH
Default Value
0
Description
When this bit is set to 1, it enables an interrupt
when ISUM ? INWV > ISUMLVL is greater than the value indicated in
ISUMLVL register.
22:21
23
Reserved
PKI
00
0
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the voltage channel has ended.
25
CRC
0
When this bit is set to 1, it enables an interrupt when the latest checksum value is
different from the checksum value computed when Run register was set to 1.
31:26
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Table 40. PHSTATUS Register (Address 0xE600)
Bit
2:0
3
4
5
8:6
9
10
11
12
Mnemonic
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
Default Value
000
0
0
0
000
0
0
0
0
Description
Reserved. These bits are always 0.
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always 0.
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
0: Phase A voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase A voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase A voltage generates Bit 16
(SAG) in the STATUS1 register.
13
VSPHASE[1]
0
0: Phase B voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase B voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase B voltage generates Bit 16
(SAG) in the STATUS1 register.
14
VSPHASE[2]
0
0: Phase C voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase C voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase C voltage generates Bit 16
(SAG) in the STATUS1 register.
15
Reserved
0
Reserved. This bit is always 0.
Table 41. PHNOLOAD Register (Address 0xE608)
Bit
0
Mnemonic
NLPHASE[0]
Default Value
0
Description
0: Phase A is out of no load condition determined by the Phase A total active power and
apparent power.
1: Phase A is in no load condition determined by phase A total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
1
NLPHASE[1]
0
0: Phase B is out of no load condition determined by the Phase B total active power and
apparent power.
1: Phase B is in no load condition determined by the Phase B total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
2
NLPHASE[2]
0
0: Phase C is out of no load condition determined by the Phase C total active power and
apparent power.
1: Phase C is in no load condition determined by the Phase C total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
3
FNLPHASE[0]
0
0: Phase A is out of no load condition based on fundamental active/reactive powers.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
Rev. A| Page 94 of 104
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