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参数资料
| 型号： | EVAL-ADF4157EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF4157 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4157 |
| 主要属性： | 单路分数-N PLL |
| 次要属性： | 6GHz |
| 已供物品： | 板 |
| 相关产品： | ADF4157BRUZ-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP ADF4157BRUZ-RL7-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP ADF4157BRUZ-RL-ND - IC PLL FREQ SYNTH 6GHZ 16TSSOP |
ADF4157
Data Sheet
Rev. D | Page 12 of 24
FRAC/INT REGISTER (R0) MAP
With R0[2:0] set to 000, the on-chip FRAC/INT register is
programmed as shown in Figure 17.
Reserved Bit
The reserved bit should be set to 0 for normal operation.
MUXOUT
The on-chip multiplexer is controlled by Bits DB[30:27] on the
ADF4157. See Figure 17 for the truth table.
12-Bit INT Value
These 12 bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 1. See the INT, FRAC, and R Relationship section
for more information.
12-Bit MSB FRAC Value
These 12 bits, along with Bits DB[27:15] in the LSB FRAC
register (R1), control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
These 12 bits are the most significant bits (MSB) of the 25-bit
FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1)
are the least significant bits (LSB). See the RF Synthesizer: A
Worked Example section for more information.
DB31
CONTROL
BITS
12-BIT MSB FRACTIONAL VALUE
(FRAC)
12-BIT INTEGER VALUE (INT)
MUXOUT
CONTROL
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
M4
M3
M2
M1
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
F25
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14 C3(0) C2(0) C1(0)
R
ESER
VED
M4
M3
M2
M1
OUTPUT
0
THREE-STATE OUTPUT
0
1
DVDD
0
1
0
DGND
0
1
R DIVIDER OUTPUT
0
1
0
N DIVIDER OUTPUT
0
1
0
1
ANALOG LOCK DETECT
0
1
0
DIGITAL LOCK DETECT
0
1
SERIAL DATA OUTPUT
1
0
RESERVED
1
0
1
RESERVED
1
0
1
0
CLK DIVIDER OUTPUT
1
0
1
RESERVED
1
0
FASTLOCK SWITCH
1
0
1
R DIVIDER/2
1
0
N DIVIDER/2
1
RESERVED
F12
F11
..........
F2
F1
MSB FRACTIONAL VALUE
(FRAC)*
0
..........
0
..........
0
1
0
..........
1
0
2
0
..........
1
3
.
..........
.
..........
.
..........
.
1
..........
0
4092
1
..........
0
1
4093
1
..........
1
0
4094
1
..........
1
4095
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
INTEGER VALUE
(INT)
0
1
0
1
23
0
1
0
24
0
1
0
1
25
0
1
0
1
0
26
.
1
0
1
4093
1
0
4094
1
4095
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
05874-
011
Figure 17. FRAC/INT Register (R0) Map
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