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参数资料
| 型号： | EVAL-ADF4252EBZ2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADF4252 NO VCO/FILTER |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4252 |
| 主要属性： | 双路分数-N PLL II |
| 次要属性： | 板不包括环路滤波器和 VCO |
| 已供物品： | 部分安装的板，线缆，软件 |
| 相关产品： | ADF4252BCPZ-R7-ND - IC PLL FREQ SYNTHESIZER 24LFCSP ADF4252BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 24LFCSP ADF4252BCPZ-ND - IC PLL FREQ SYNTHESIZER 24-LFCSP |
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REV. B
ADF4252
–23–
IF Counter Reset
DB3 is the IF counter reset bit for the ADF4252. When this is
1, the IF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
IF Charge Pump Three-State
This bit puts the IF charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
IF Power-Down
DB5 on the ADF4252 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on the IF
section. Setting this bit to 0 will return the section to normal
operation. While in software power-down, the part will retain all
information in its registers. Only when supplies are removed will
the register contents be lost.
When a power-down is activated, the following events occur:
1. All active IF dc current paths are removed.
2. The IF synthesizer counters are forced to their load state
conditions.
3. The IF charge pump is forced into three-state mode.
4. The IF digital lock detect circuitry is reset.
5. The IFIN input is debiased.
6. The input register remains active and capable of loading and
latching data.
IF Phase Detector Polarity
DB7 in the ADF4252 sets the IF phase detector polarity. When
the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
IF Charge Pump Current Setting
DB8, DB9, and DB10 set the IF charge pump current setting.
This should be set to whatever charge pump current the loop
filter has been designed with (see Table VII).
IF Test Modes
These bits should be set to [0, 0] for normal operation.
RF Phase Resync
Setting the phase resync bits [15, 14, 11] to [1, 1, 1] enables
the phase resync feature. With a fractional modulus of M, a
fractional-N PLL can settle with any one of (2
)/M valid
phase offsets with respect to the reference input. This is different
to integer-N (where the RF output always settles to the same
static phase offset with respect to the input reference, which is
zero ideally) but does not matter in most applications where all
that is required is consistent frequency lock.
For applications where a consistent phase relationship between
the output and reference is required (i.e., digital beamforming),
the ADF4252 fractional-N synthesizer can be used with the phase
resync feature enabled. This ensures that if the user programs
the PLL to jump from Frequency (and Phase) A to Frequency
(and Phase) B and back again to Frequency A, the PLL will return
to the original phase (Phase A).
When enabled, it will activate every time the user programs
Register R0 or R1 to set a new output frequency. However if a
cycle slip occurs in the settling transient after the phase re-resync
operation, the phase resync will be lost. This can be avoided by
delaying the resync activation until the locking transient is close
to its final frequency. In the IF R divider register, Bits R5[17–3]
are used to set a time interval from when the new channel is pro-
grammed to the time the resync is activated. Although the time
interval resolution available from the 15-bit IF R register is one
REFIN clock cycle, IF R should be programmed to be a value that
is an integer multiple of the programmed MOD value to set a
time interval that is at least as long as the RF PLL loop’s lock time.
For example, if REFIN = 26 MHz, MOD = 130 to give 200 kHz
output steps (FRES), and the RF loop has a settling time of 150
s,
then IF_R should be programmed to 3900, as
26
150
3900
MHz
s
×=
Note that if it is required to use the IF synthesizer with phase
resync enabled on the RF synth, the IF synth must operate with
a PFD frequency of 26 MHz/3900. In an application where the
IF synth is not required, the user should ensure that Registers
R4 and R6 are not programmed so that the rest of the IF circuitry
remains in power-down.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially applying power to the supply pins, there are three
ways to operate the device.
RF and IF Synthesizers Operational
All registers must be written to when powering up both the RF
and IF synthesizer.
RF Synthesizer Operational, IF Power-Down
It is necessary to write only to Registers R3, R2, R1, and R0
when powering up the RF synthesizer only. The IF side will
remain in power-down until Registers R6, R5, R4, and R3 are
written to.
IF Synthesizer Operational, RF Power-Down
It is necessary to write to only Registers R6, R5, R4, and R3 when
powering up the IF synthesizer only. The RF side will remain in
power-down until registers R3, R2, R1, and R0 are written to.
RF Synthesizer: An Example
The RF synthesizer should be programmed as follows:
RF
INT
FRAC
MOD
F
OUT
PFD
=+
×
(4)
where RFOUT = the RF frequency output, INT = the integer division
factor, FRAC = the fractionality, and MOD = the modulus.
F
REF
D
R
PFD
IN
=×
+
1
(5)
where REFIN = the reference frequency input, D = the RF
REFIN doubler bit, and R = the RF reference division factor.
For example, in a GSM 1800 system where 1.8 GHz RF frequency
output (RFOUT) is required, a 13 MHz reference frequency input
(REFIN) is available and a 200 kHz channel resolution (FRES) is
required on the RF output.
MOD
REF
F
MOD
IN
RES
=
==
13
200
65
MHz
kHz
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