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参数资料
| 型号： | EVAL-ADF4351EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | BOARD 1 EVAL FOR ADF4351 |
| 标准包装： | 1 |
| 系列： | * |
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ADF4351
Data Sheet
Rev. 0 | Page 18 of 28
REGISTER 0
Control Bits
When Bits[C3:C1] are set to 000, Register 0 is programmed.
Figure 24 shows the input data format for programming this
register.
16-Bit Integer Value (INT)
The 16 INT bits (Bits[DB30:DB15]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 1 (see the INT, FRAC, MOD, and
R Counter Relationship section). Integer values from 23 to
65,535 are allowed for the 4/5 prescaler; for the 8/9 prescaler,
the minimum integer value is 75.
12-Bit Fractional Value (FRAC)
The 12 FRAC bits (Bits[DB14:DB3]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC values from 0 to (MOD 1)
cover channels over a frequency range equal to the PFD refer-
ence frequency.
REGISTER 1
Control Bits
When Bits[C3:C1] are set to 001, Register 1 is programmed.
Figure 25 shows the input data format for programming this
register.
Phase Adjust
The phase adjust bit (Bit DB28) enables adjustment of the output
phase of a given output frequency. When phase adjustment is
enabled (Bit DB28 is set to 1), the part does not perform VCO
band selection or phase resync when Register 0 is updated.
When phase adjustment is disabled (Bit DB28 is set to 0), the
part performs VCO band selection and phase resync (if phase
resync is enabled in Register 3, Bits[DB16:DB15]) when Register 0
is updated. Disabling VCO band selection is recommended only
for fixed frequency applications or for frequency deviations of
<1 MHz from the originally selected frequency.
Prescaler Value
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD values, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(DB27) in Register 1 sets the prescaler value.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 3.6 GHz. Therefore,
when operating the ADF4351 above 3.6 GHz, the prescaler must
be set to 8/9. The prescaler limits the INT value as follows:
Prescaler = 4/5: NMIN = 23
Prescaler = 8/9: NMIN = 75
12-Bit Phase Value
Bits[DB26:DB15] control the phase word. The phase word must
be less than the MOD value programmed in Register 1. The phase
word is used to program the RF output phase from 0° to 360°
with a resolution of 360°/MOD (see the Phase Resync section).
In most applications, the phase relationship between the RF
signal and the reference is not important. In such applications,
the phase value can be used to optimize the fractional and sub-
fractional spur levels. For more information, see the Spur
If neither the phase resync nor the spurious optimization func-
tion is used, it is recommended that the phase word be set to 1.
12-Bit Modulus Value (MOD)
The 12 MOD bits (Bits[DB14:DB3]) set the fractional modulus.
The fractional modulus is the ratio of the PFD frequency to the
channel step resolution on the RF output. For more information,
see the 12-Bit Programmable Modulus section.
REGISTER 2
Control Bits
When Bits[C3:C1] are set to 010, Register 2 is programmed.
Figure 26 shows the input data format for programming this
register.
Low Noise and Low Spur Modes
The noise mode on the ADF4351 is controlled by setting
Bits[DB30:DB29] in Register 2 (see Figure 26). The noise mode
allows the user to optimize a design either for improved spurious
performance or for improved phase noise performance.
When the low spur mode is selected, dither is enabled. Dither
randomizes the fractional quantization noise so that it resembles
white noise rather than spurious noise. As a result, the part is
optimized for improved spurious performance. Low spur mode
is normally used for fast-locking applications when the PLL
closed-loop bandwidth is wide. Wide loop bandwidth is a loop
bandwidth greater than 1/10 of the RFOUT channel step resolu-
tion (fRES). A wide loop filter does not attenuate the spurs to the
same level as a narrow loop bandwidth.
For best noise performance, use the low noise mode option.
When the low noise mode is selected, dither is disabled. This
mode ensures that the charge pump operates in an optimum
region for noise performance. Low noise mode is extremely
useful when a narrow loop filter bandwidth is available. The
synthesizer ensures extremely low noise, and the filter attenuates
the spurs. Figure 10 through Figure 12 show the trade-offs in a
typical W-CDMA setup for different noise and spur settings.
MUXOUT
The on-chip multiplexer is controlled by Bits[DB28:DB26]
(see Figure 26). Note that N counter output must be disabled
for VCO band selection to operate correctly.
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