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参数资料
| 型号： | EVAL-ADM1186-1MBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | KIT MICRO EVALUATION ADM1186-1 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADM1186-1 |
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Data Sheet
THEORY OF OPERATION
The operation of the ADM1186 is described in the following
sections. Where necessary, differences between the ADM1186-1
and the ADM1186-2 are noted. Figure 29 is a detailed functional
block diagram of the ADM1186-1, and Figure 31 is a detailed
functional block diagram of the ADM1186-2.
The operation of the ADM1186 is described in the context of a
typical voltage monitoring and sequencing application, as shown
in Figure 1. This example uses the ADM1186-1, because it is
essentially a superset of the functionality of the ADM1186-2. In
the example application, the ADM1186-1 turns on four regulators,
monitors four separate voltage rails, and generates a power-good
signal to turn on a microcontroller when all power supplies are
on and above their UV threshold level. Figure 35 shows a typical
ADM1186-2 voltage sequencing and monitoring application.
UVLO BEHAVIOR
The ADM1186 is designed to ensure that the outputs are always
in a known state for a V CC supply voltage of 1 V or greater; if the
V CC supply voltage is below 1 V, the state of the outputs is not
guaranteed. Figure 25 shows the behavior of the outputs over
the full V CC supply range.
V CC
5.5V
UNDER STATE
MACHINE CONTROL
2.7V
V UVLO
ADM1186
After the fault hold time elapses, the state machine moves to the
CLEAR FAULT state. If the UP (ADM1186-1) or UP/DOWN
(ADM1186-2) pin is low, the state machine can exit the CLEAR
FAULT state. This change is indicated on the ADM1186-1 by
the FAULT pin being asserted high. For the ADM1186-2, there
is no external indication that the part is ready to perform
sequencing, so 0.5 ms should be allowed after V CC comes up
before attempting to start a power-up sequence.
POWER-UP SEQUENCING AND MONITORING
In the example shown in Figure 1, the main supply of 3.3 V
powers up the device via the VCC pin. The state machine remains
in the WAIT START state until either a rising edge on the UP
pin initiates a power-up sequence, or a fault condition occurs.
The ADM1186-2 requires a rising edge on the UP/DOWN pin
to start a power-up sequence.
If a rising edge on the UP pin is detected, the state machine
moves to the DELAY 1 state. The ADM1186-2 does not have a
shows the ADM1186-1 state machine in detail; Figure 32 shows
the ADM1186-2 state machine. The waveforms for a typical
power-up and power-down sequence when no faults occur are
shown in Figure 33 (ADM1186-1) and Figure 34 (ADM1186-2).
In the DELAY 1 state, a time delay, set by the capacitor
connected to the DLY_EN_OUT1 pin, is allowed to elapse.
Then, in the ENABLE OUT1 state, the OUT1 pin is asserted
high. OUT1 is an open-drain, active high output, and in this
application it enables the output of a 2.5 V regulator.
During the ENABLE OUT1 state, the VIN1 pin monitors the
UVLO
ALL OUTPUTS
LOW
2.5 V supply after a blanking delay, set by the capacitor on the
BLANK_DLY pin. The blanking delay, which is the same for all
1V
ACTIVE
OUTPUTS
supplies, is set to allow the slowest rising supply sufficient time
to switch on.
NOT GUARANTEED
0V
Figure 25. ADM1186 Output Behavior over V CC Supply
As the V CC supply begins to rise, an undervoltage lockout (UVLO)
circuit becomes active and begins to pull the outputs of the
ADM1186 low. The outputs are not guaranteed to be low until
the V CC supply has reached 1 V. State machine operation is also
disabled, so it is not possible to initiate a power-up sequence.
This behavior ensures that enable pins on dc-to-dc converters
or point-of-load (POL) devices connected to the OUTx pins are
An external resistor divider scales the supply voltage down for
monitoring at the VIN1 pin (see Figure 26). The resistor ratio is
selected so that the VIN1 voltage is 0.6 V when the supply voltage
rises to the UV level at start-up (a voltage below the nominal 2.5 V
level). In Figure 26, R1 is 7.4 kΩ and R2 is 2.5 kΩ, so a voltage
level of 2.375 V corresponds to 0.6 V on the noninverting input
of the first comparator.
V
2.5V
2.375V
held low as the supplies are rising. This prevents the dc-to-dc
converters or the POLs from switching on briefly and then
switching off as the supply rails stabilize.
When V CC rises above V UVLO and the internal reference is stable,
0V
2.375V SUPPLY
GIVES 0.6V
AT VIN1 PIN
t
R1
7.4k ?
VIN1
R2
2.5k ?
0.6V
ADM1186
TO LOGIC
CORE
the UVLO circuit enables the state machine. The state machine
takes control of the outputs and begins operation from the SET
FAULT state.
Rev. B | Page 13 of 28
Figure 26. Setting the Undervoltage Threshold
with an External Resistor Divider
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| EVAL-ADM1186-2EBZ | 功能描述:KIT EVALUATION FOR ADM1186-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADM1186-2MBZ | 功能描述:KIT MICRO EVALUATION ADM1186-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
| EVAL-ADM1191EBZ | 功能描述:BOARD EVALUATION FOR ADM1191 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADM1191EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Digital Power Monitor with Convert Pin and ALERTB O |
| EVAL-ADM1192EBZ | 功能描述:BOARD EVALUATION FOR ADM1192 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
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