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参数资料
| 型号： | EVAL-ADM1186-1MBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | KIT MICRO EVALUATION ADM1186-1 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADM1186-1 |
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ADM1186
CASCADING MULTIPLE DEVICES
Multiple ADM1186-1 devices can be cascaded in applications
that require more than four supplies to be sequenced and
monitored. When ADM1186-1 devices are cascaded, the
controlled power-up and power-down of all the cascaded
supplies is maintained using only three pins on each device.
There are several configurations for interconnecting these
devices. The most suitable configuration depends on the
application. Figure 36 and Figure 37 show two methods for
cascading multiple ADM1186-1 devices.
used for timing are not shown in the figure for clarity. To ensure
controlled power-up and power-down sequencing of all 12 sup-
plies, the following connections are made:
Data Sheet
each with common status outputs. In this example, both devices
share the same sequence control signal, so they start their
power-up and power-down sequences at the same time. Both
devices must complete their power-up sequences before the
POWER GOOD signal goes high.
The FAULT pins of all devices in a cascade should be connected.
Connecting the FAULT pins ensures that an undervoltage fault
on one device, or an unexpected event such as a rising or falling
edge on the UP or DOWN pin, generates a fault condition on
all the other devices.
When an internal fault condition occurs on a device, it pulls its
FAULT pin low. This in turns causes the other ADM1186-1
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The UP pin of the first device and the DOWN pin of the
last device in the cascade chain are connected.
The SEQ_DONE pin of Device N is connected to the UP
pin of Device N + 1.
The SEQ_DONE pin of Device N is connected to the
DOWN pin of Device N ? 1.
devices to enter the SET FAULT state and pull their FAULT pins
low. Each device waits for the fault hold time to elapse and then
moves to the CLEAR FAULT state.
If the V CC supply for an ADM1186-1 drops below V UVLO , the
UVLO circuit becomes active, and the FAULT pin is pulled low.
This generates a fault condition on all other connected devices.
When the SEQUENCE CONTROL line goes high, Device A
begins the power-up sequence, turning on each enable output
in turn, with the associated delays, according to the state
machine. When Device A completes its power-up sequence, the
SEQ_DONE pin goes from low to high, initiating a power-up
sequence on Device B. When Device B completes its power-up
sequence, the Device B SEQ_DONE pin goes high, initiating a
power-up sequence on Device C. When Device C completes its
power-up sequence and all supplies are above the UV threshold,
the system POWER GOOD signal goes high.
If the SEQUENCE CONTROL line goes low, Device C starts a
power-down sequence, turning off its enable outputs. When all
Device C enable outputs are off, the SEQ_DONE pin on Device C
goes low, causing a high-to-low transition on the DOWN pin of
Device B. This transition initiates a power-down sequence on
Device B, which takes all its OUTx pins low, causing SEQ_DONE
to be taken low. This high-to-low transition is seen by Device A,
which starts its power-down sequence, thus completing the
ordered shutdown of the 12 supplies.
Note that the capacitor on the DLY_EN_OUT1 pin of Device B
(not shown in Figure 36) sets the sequence time delay between
A device in the CLEAR FAULT state holds its FAULT pin low
until its UP input pin is low. The device then moves into the
WAIT ALL OK state and releases the FAULT pin.
If, for example, a UV fault occurs on a VINx pin during a
power-up sequence, the UP pin will be high on the first device
in the cascade. The first device in the cascade holds the FAULT
line low until the UP pin is brought low. All other devices will
have released their FAULT pins and will be in the WAIT ALL
OK state.
When the UP pin goes low, the first device releases its FAULT
pin so the FAULT line returns high, which allows all devices to
move together from the WAIT ALL OK state back into the
WAIT START state, ready for the next power-up sequence.
An external device such as a microcontroller, field programmable
gate array (FPGA), or an overtemperature sensor can cause a
fault condition by briefly bringing FAULT low. In this case, the
ADM1186-1 behaves as described. If the external device continues
to hold the FAULT line low, all the ADM1186-1 devices remain
in the WAIT ALL OK state, effectively preventing a power-up
sequence from starting.
the last supply of Device A and the first supply of Device B
being turned on and off.
Rev. B | Page 24 of 28
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| EVAL-ADM1186-2EBZ | 功能描述:KIT EVALUATION FOR ADM1186-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADM1186-2MBZ | 功能描述:KIT MICRO EVALUATION ADM1186-2 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
| EVAL-ADM1191EBZ | 功能描述:BOARD EVALUATION FOR ADM1191 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADM1191EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Digital Power Monitor with Convert Pin and ALERTB O |
| EVAL-ADM1192EBZ | 功能描述:BOARD EVALUATION FOR ADM1192 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
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