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| 型号： | EVAL-ADUM3471EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/36页 |
| 文件大小： | 0K |
| 描述： | EVALUATION MODULE FOR ADUM3471 |
| 标准包装： | 1 |
| 系列： | iCoupler® |
| 主要目的： | 接口，数字式隔离器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADuM3470，ADuM3471，ADuM3472，ADuM3473，ADuM3474 |
| 主要属性： | 2 个独立的 ADuM347x 电路 |
| 次要属性： | 3.3 V ~ 5.5 V 电源 |
| 已供物品： | 板 |
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ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
Parameter
I/O Input Currents
Symbol
I IA , I IB , I IC , I ID
Min
?20
Typ
+0.01
Max
+20
Unit
μA
Test Conditions/Comments
Logic High Input Threshold
Logic Low Input Threshold
V IH
V IL
2.0
0.8
V
V
Logic High Output Voltages
V OAH , V OBH ,
V DD1 ? 0.3,
5.0
V
I Ox = ?20 μA, V Ix = V IxH
V OCH , V ODH
V ISO ? 0.3
V DD1 ? 0.5,
4.8
V
I Ox = ?4 mA, V Ix = V IxH
V ISO ? 0.5
Logic Low Output Voltages
V OAL , V OBL ,
0.0
0.1
V
I Ox = 20 μA, V Ix = V IxL
V OCL , V ODL
0.0
0.4
V
I Ox = 4 mA, V Ix = V IxL
AC SPECIFICATIONS
A Grade
C L = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
PW
1
1000
ns
Mbps
Propagation Delay
Pulse Width Distortion, |t PLH ? t PHL |
Propagation Delay Skew
Channel-to-Channel Matching
t PHL , t PLH
PWD
t PSK
t PSKCD /t PSKOD
55
100
40
50
50
ns
ns
ns
ns
C Grade
C L = 15 pF, CMOS signal levels
Minimum Pulse Width
Maximum Data Rate
PW
25
40
ns
Mbps
Propagation Delay
Pulse Width Distortion, |t PLH ? t PHL |
t PHL , t PLH
PWD
30
45
60
8
ns
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew
t PSK
15
ns
Channel-to-Channel Matching
Codirectional Channels
Opposing Directional Channels
t PSKCD
t PSKOD
8
15
ns
ns
Output Rise/Fall Time (10% to 90%)
t R /t F
2.5
ns
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
V CM = 1000 V, transient
magnitude = 800 V
At Logic High Output
At Logic Low Output
Refresh Rate
|CM H |
|CM L |
f r
25
25
35
35
1.0
kV/μs
kV/μs
Mbps
V Ix = V DD1 or V ISO
V Ix = 0 V
1
2
3
4
The contributions of supply current values for all four channels are combined at identical data rates.
The V ISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the V ISO power budget.
The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
This current is available for driving external loads at the V ISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.
Rev. A | Page 10 of 36
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