参数资料
型号: EVAL-ADUM3471EBZ
厂商: Analog Devices Inc
文件页数: 30/36页
文件大小: 0K
描述: EVALUATION MODULE FOR ADUM3471
标准包装: 1
系列: iCoupler®
主要目的: 接口,数字式隔离器
嵌入式:
已用 IC / 零件: ADuM3470,ADuM3471,ADuM3472,ADuM3473,ADuM3474
主要属性: 2 个独立的 ADuM347x 电路
次要属性: 3.3 V ~ 5.5 V 电源
已供物品:
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474
Data Sheet
POWER CONSUMPTION
The V DD1 power supply provides power to the i Coupler data
channels, as well as to the power converter. For this reason,
the quiescent currents drawn by the power converter and the
primary and secondary I/O channels cannot be determined
separately. All of these quiescent power demands are combined
in the I DD1 (Q) current (see the simplified diagram in Figure 45).
The total I DD1 supply current is equal to the sum of the quiescent
operating current; the dynamic current, I DD1 (D) , demanded by
the I/O channels; and any external I ISO load.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of I DD1 and I ISO (LOAD) .
POWER CONSIDERATIONS
Soft Start Mode and Current-Limit Protection
When the ADuM347x device first receives power from V DD1 , it is
in soft start mode, and the output voltage, V ISO , is increased
gradually while it is below the start-up threshold. In soft start
mode, the width of the PWM signal is increased gradually by
the primary converter to limit the peak current during V ISO
I DD1 (Q)
I DD1 (D)
PRIMARY
CONVERTER
I DDP (D)
FB
SECONDARY
CONTROLLER
I ISO (D)
I ISO
power-up. When the output voltage is larger than the start-up
threshold, the PWM signal can be transferred from the second-
ary controller to the primary converter, and the dc-to-dc converter
switches from soft start mode to the normal PWM control mode.
If a short circuit occurs, the push-pull converter shuts down for
PRIMARY
DATA
I/O
4CH
SECONDARY
DATA
I/O
4CH
approximately 2 ms and then enters soft start mode. If, at the end
of soft start, a short circuit still exists, the process is repeated,
which is called hiccup mode. If the short circuit is cleared, the
ADuM347x device enters normal operation.
Figure 45. Power Consumption Within the ADuM347x
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of f r . The dynamic current
of each channel is determined by its data rate. Figure 18 and
Figure 22 show the current for a channel in the forward direction,
meaning that the input is on the primary side of the part. Figure 19
and Figure 23 show the current for a channel in the reverse direc-
tion, meaning that the input is on the secondary side of the part.
Figure 18, Figure 19, Figure 22, and Figure 23 assume a typical
15 pF output load.
The following relationship allows the total I DD1 current to be
I DD1 = ( I ISO × V ISO )/( E × V DD1 ) + Σ I CHn ; n = 1 to 4 (1)
where:
I DD1 is the total supply input current.
I ISO is the current drawn by the secondary side external load.
E is the power supply efficiency at the given output load from
Figure 13 or Figure 17 at the V ISO and V DD1 condition of interest.
I CHn is the current drawn by a single channel, determined from
Figure 18, Figure 19, Figure 22, or Figure 23, depending on
channel direction.
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
I ISO (LOAD) = I ISO (MAX) ? Σ I ISO (D)n ; n = 1 to 4 (2)
where:
I ISO (LOAD) is the current available to supply an external secondary
side load.
I ISO (MAX) is the maximum external secondary side load current
available at V ISO .
I ISO (D)n is the dynamic load current drawn from V ISO by an
The ADuM347x devices also have a pulse-by-pulse current
limit, which is active in startup and normal operation. This
current limit protects the primary switches, X1 and X2, from
exceeding approximately 1.2 A peak and also protects the
transformer windings.
Data Channel Power Cycle
The ADuM347x data input channels on the primary side and
the data input channels on the secondary side are protected from
premature operation by UVLO circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive,
and all input channel drivers and refresh circuits are idle. Outputs
are held in a low state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to V DD1 , the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that time,
the data channels are initialized to their default low output state
until they receive data pulses from the secondary side.
The primary side input channels sample the input and send a
pulse to the inactive secondary output. The secondary side
converter begins to accept power from the primary, and the V ISO
voltage starts to rise. When the secondary side UVLO is reached,
the secondary side outputs are initialized to their default low state
until data, either a transition or a dc refresh pulse, is received from
the corresponding primary side input. It can take up to 1 μs after
the secondary side is initialized for the state of the output to
correlate with the primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid one propagation delay after the
secondary side becomes active.
output or input channel, as shown for a single supply in Figure 20
or Figure 21 or for a double supply in Figure 24 or Figure 25.
Rev. A | Page 30 of 36
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