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参数资料
| 型号： | EVB3020A-IFBD |
| 英文描述： | GSM Multiband RF Transceiver |
| 中文描述： | 手机多频段射频收发器 |
| 文件页数： | 16/44页 |
| 文件大小： | 409K |
| 代理商： | EVB3020A-IFBD |
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Advance Data Sheet
December 1999
W3020 GSM Multiband RF Transceiver
Lucent Technologies Inc.
23
Programming Information (continued)
TR Register (continued)
Table 15. MO[3:1]: Mode Control
MO3
MO2
MO1
Function
Bit 22
Bit 21
Bit 20
0
Sleep: All Modules Powerdown
0
1
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
TX PLL Settling Mode (LO1, LO2, TX LO1, and TX LO2 buffers on)
1
0
1
RX PLL Settling Mode (LO1, LO2, RX LO1, and RX LO2 buffers on)
1
0
TX ON (TX modulator and mixer, LO1, LO2, TX LO1, and TX LO2 buffers on)
1
RX ON (RX mixer; LNA, if enabled; IF amplifier; LO1; LO2; RX LO1; and RX LO2
buffers on)*
*If MO bits are set to 111 with the dc correction skip bit low, a dc offset calibration cycle is performed automatically.
Table 16. T6: LO2 Disable
If this bit is set high, the 540 MHz LO2 input buffer
and LO2 PLL will be turned off. This bit will also
disable the 13 MHz clock buffer going to the
baseband amplifier correction circuits. This bit is
provided for testing purposes.
T6
Bit 19
Function
0
LO2 Circuit Enabled
1
LO2 Circuit Disabled
Table 17. T5: LO1 Disable
The T5 bit disables the LO1 circuitry including the
UHF LO1 buffer and bias circuit. This bit is provided
for testing purposes.
T5
Bit 18
Function
0
LO1 Circuitry Enabled
1
LO1 Circuitry Disabled
Table 18. T4: Receive IF Duty Cycle Corrector
Disable
When high, disables duty cycle correction circuit in
the LO2 divide-by-2 circuit for the receive IF
demodulator. This is provided for testing purposes.
T4
Bit 17
Function
0
Divide-by-2 Duty Cycle Corrector Enabled
1
Divide-by-2 Duty Cycle Corrector Disabled
Table 19. T3: Divide-by-3 Duty Cycle Corrector
Disable
When high, disables duty cycle correction circuit in
the GSM1800/1900 transmit IF LO divide-by-3
circuit. This is provided for testing purposes.
T3
Bit 16
Function
0
Divide-by-3 Duty Cycle Corrector Enabled
1
Divide-by-3 Duty Cycle Corrector Disabled
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