
15
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FA5502P/M
ZP
frequency
voltage
gain[dB]
G1
Fig.8 Voltage gain of CUR.AMP
(4) PWM comparator
Fig.9 shows the configuration of PWM comparator.
Oscillator output VCT and current error amplifier output
VIFB are compared. While VCT < VIFB, PWM
comparator output goes High and OUT pin also goes
High. Note that, during the oscillator discharge period,
OUT pin is forced to be Low, thereby determining the
maximum duty cycle. (see characteristics curve).
CS pin (pin 11) is a soft start pin. When start up, an
internal
constant
current
(11A
(typ.))
charges
capacitor C4 for soft start. Priority is given to VCS or
VIFB
whichever
is
lower.
Fig.10
shows
PWM
comparator timing chart.
11
11A
CS
Oscillator output
(CT pin)
CUR.AMP output
(IFB pin)
C4
Output
circuit
VCT
VIFB
VCS
PWM.COMP
7.5V
Fig.9 PWM comparator circuit
VCT
VCS
VIFB
OUT
pin
Normal operation
t
VCT
VCS
VIFB
OUT
pin
Operation with Dmax
t
Fig.10 PWM comparator timing chart
(5) Multiplier
The multiplier generates a current reference signal.
The rectified line voltage is divided down by resistor
and monitored by VDET pin (pin 3). Considering the
dynamic range of multiplier, design the R6 and R7 in
Fig.11 so that the peak voltage at VDET pin within a
range from 0.65V to 2.4V over the entire range of line
voltage. VFB pin is normally above 1.55V and, at this
status, multiplier output voltage Vm is approximately
expressed by:
VDET
VFB
V
)
55
.
1
V
(
K
25
.
1
Vm
×
×
=
(8)
Where
K: Output voltage factor (multiplier section)
When VFB pin is lower than 1.55V, compensation
circuit for light load operates.
As shown in Fig.7, Vm is applied via a resistor of
11 k
to inverting input (IIN-) of current error amplifier
CUR.
AMP. (For input/output characteristics of
multiplier, see characteristics curve.)
ER.AMP output
(VFB pin)
MUL
3
VVFB
VVDET
VDET
Vm
VIN
R7
R6
Fig.11 Multiplier circuit