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| 型号： | FAN3100CSX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC GATE DRVR SGL CMOS 2A SOT23-5 |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 |
| 特色产品： | FANxx Series of High-Speed, Low-Side Gate Drivers |
| 标准包装： | 1 |
| 配置： | 低端 |
| 输入类型： | 差分 |
| 延迟时间： | 15ns |
| 电流 - 峰： | 3A |
| 配置数： | 1 |
| 输出数： | 1 |
| 电源电压： | 4.5 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-23-5 |
| 包装： | 标准包装 |
| 产品目录页面： | 1214 (CN2011-ZH PDF) |
| 其它名称： | FAN3100CSXDKR |
Applications Information
Input Thresholds
The FAN3100 offers TTL or CMOS input thresholds. In
the FAN3100T, the input thresholds meet industry-
standard TTL logic thresholds, independent of the V DD
voltage, and there is a hysteresis voltage of
approximately 0.4V. These levels permit the inputs to be
driven from a range of input logic signal levels for which
a voltage over 2V is considered logic high. The driving
signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6V/μs or faster, so the
rise time from 0 to 3.3V should be 550ns or less. With
reduced slew rate, circuit noise could cause the driver
input voltage to exceed the hysteresis voltage and
retrigger the driver input, causing erratic operation.
In the FAN3100C, the logic input thresholds are
dependent on the V DD level and, with V DD of 12V, the
logic rising edge threshold is approximately 55% of V DD
and the input falling edge threshold is approximately
38% of V DD . The CMOS input configuration offers a
hysteresis voltage of approximately 17% of V DD . The
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the I DD (static) typical performance graphs (Figure 9 -
Figure 10 and Figure 15 - Figure 16), the curve is
produced with all inputs floating (OUT is low) and
indicates the lowest static I DD current for the tested
configuration. For other states, additional current flows
through the 100k Ω resistors on the inputs and outputs
shown in the block diagrams (see Figure 5 - Figure 6).
In these cases, the actual static I DD current is the value
obtained from the curves plus this additional current.
MillerDrive? Gate Drive Technology
FAN3100 drivers incorporate the MillerDrive?
architecture shown in Figure 42 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a wide range of supply
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between 1/3
to 2/3 V DD and the MOS devices pull the output to the
high or low rail.
The purpose of the MillerDrive? architecture is to speed
up switching by providing the highest current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
? 2007 Fairchild Semiconductor Corporation
FAN3100 ? Rev. 1.0.4
14
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched on.
The output pin slew rate is determined by V DD voltage
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
Figure 42. MillerDrive? Output Architecture
Under-Voltage Lockout
The FAN3100 start-up logic is optimized to drive ground
referenced N-channel MOSFETs with a under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When V DD is rising, yet below the
3.9V operational level, this circuit holds the output low,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2V before the
part shuts down. This hysteresis helps prevent chatter
when low V DD supply voltages have noise from the
power switching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver would turn the P-channel
MOSFET on with V DD below 3.9V.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor C BYP with low
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
is in addition to bulk electrolytic capacitance of 10μF to
47μF often found on driver and controller bias circuits.
A typical criterion for choosing the value of C BYP is to
keep the ripple voltage on the V DD supply ≤ 5%. Often
this is achieved with a value ≥ 20 times the equivalent
load capacitance C EQV , defined here as Q gate /V DD .
Ceramic capacitors of 0.1μF to 1μF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
If circuit noise affects normal operation, the value of
C BYP may be increased to 50-100 times the C EQV , or
C BYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF, mounted
www.fairchildsemi.com
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