参数资料
型号: FAN3100CSX
厂商: Fairchild Semiconductor
文件页数: 15/22页
文件大小: 0K
描述: IC GATE DRVR SGL CMOS 2A SOT23-5
产品变化通告: Mold Compound Change 12/Dec/2007
特色产品: FANxx Series of High-Speed, Low-Side Gate Drivers
标准包装: 1
配置: 低端
输入类型: 差分
延迟时间: 15ns
电流 - 峰: 3A
配置数: 1
输出数: 1
电源电压: 4.5 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
产品目录页面: 1214 (CN2011-ZH PDF)
其它名称: FAN3100CSXDKR
closest to the VDD and GND pins to carry the higher-
frequency components of the current pulses.
Layout and Connection Guidelines
The FAN3100 incorporates fast reacting input circuits,
short propagation delays, and powerful output stages
capable of delivering current peaks over 2A to facilitate
voltage transition times from under 10ns to over 100ns.
The following layout and connection guidelines are
strongly recommended:
Figure 43. Current Path for MOSFET Turn-On
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Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logic thresholds.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.
The FAN3100 is available in two packages with
slightly different pinouts, offering similar
performance. In the 6-pin MLP package, Pin 2 is
internally connected to the input analog ground and
should be connected to power ground, Pin 5,
through a short direct path underneath the IC. In the
5-pin SOT23, the internal analog and power ground
connections are made through separate, individual
bond wires to Pin 2, which should be used as the
common ground point for power and control signals.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all pins
as short and direct as possible.
The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
Figure 43 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, C BYP , and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized C BYP acts to
contain the high peak current pulses within this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
? 2007 Fairchild Semiconductor Corporation
FAN3100 ? Rev. 1.0.4
15
www.fairchildsemi.com
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