参数资料
型号: FAN3268TMX
厂商: Fairchild Semiconductor
文件页数: 13/17页
文件大小: 0K
描述: IC BRIDGE DVR P/N-CH 2A 8SOIC
标准包装: 1
配置: 半桥
输入类型: 反相和非反相
延迟时间: 14ns
电流 - 峰: 3A
配置数: 1
输出数: 2
电源电压: 4.5 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 标准包装
其它名称: FAN3268TMXDKR
Layout and Connection Guidelines
The FAN3268 gate driver incorporates fast-reacting
input circuits, short propagation delays, and powerful
output stages capable of delivering current peaks over
2 A to facilitate voltage transition times from under 10ns
to over 150 ns. The following layout and connection
Operational Waveforms
Figure 28 shows startup waveforms for non-inverting
channel A. At power-up, the driver output for channel A
remains low until the V DD voltage reaches the UVLO turn-
on threshold, then OUTA operates in-phase with INA.
guidelines are strongly recommended:
? Keep high-current output and power ground paths
separate from l ogic and enable input signals and
signal ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
?
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
?
If the inputs to a channel are not externally
connected, the internal 100 k ? resistors indicated
VDD
INA
OUTA
UVLO
Turn-on threshold
on block diagrams command a low output (channel
A) or a high output (channel B). In noisy
environments, it may be necessary to tie inputs or
enables of an unused channel to VDD or GND
using short traces to prevent noise from causing
spurious output switching.
Figure 28. Non-Inverting Startup Waveforms
Figure 29 illustrates startup waveforms for inverting
channel B. At power-up, the driver output for channel B
is tied to V DD through an internal 100 kΩ resistor until
the V DD voltage reaches the UVLO turn-on threshold,
?
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
then OUTB operates out of phase with INB.
?
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
best results, make connections to all pins as short
and direct as possible.
The turn-on and turn-off current paths should be
minimized.
VDD
INB
UVLO
Turn-on threshold
OUTB
Figure 29. Inverting Startup Waveforms
? 2009 Fairchild Semiconductor Corporation
FAN3268 ? Rev. 1.0.3
13
www.fairchildsemi.com
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