参数资料
型号: FAN5056V90M
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO24
封装: SOIC-24
文件页数: 5/19页
文件大小: 266K
代理商: FAN5056V90M
FAN5056V85/FAN5056V90
REV. 0.8.0 1/31/01
13
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Specication
Application Information
The FAN5056 Controller
The FAN5056 is a programmable synchronous DC-DC con-
troller IC. When designed around the appropriate external
components, the FAN5056 can be congured to deliver more
than 45A of output current, as appropriate for Intel’s
VRM8.5 nd VRM9.0, and other processors. The FAN5056
functions as a xed frequency PWM step down regulator.
Main Control Loop
Refer to the FAN5056 Block Diagram on page 1. The
FAN5056 implements “summing mode control,” which is
different from both classical voltage-mode and current-mode
control. It provides superior performance to either by allowing
a large converter bandwidth over a wide range of output loads.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog section consists of signal conditioning ampliers
feeding into a comparator which provides the input to the
digital control block. The signal conditioning section accepts
input from the DROOP (current feedback) and VFB (voltage
feedback) pins and sets up two controlling signal paths. The
rst, the voltage control path, amplies the difference
between the VFB signal and the reference voltage from the
DAC and presents the output to one of the summing amplier
inputs. The second, current control path, takes the difference
between the DROOP and SW pins when the high-side
MOSFET is on, reproducing the voltage across the MOSFET
and thus the input current; it presents the resulting signal to
another input of the summing amplier. These two signals are
then summed together. This output is then presented to a com-
parator looking at the oscillator ramp, which provides the
main PWM control signal to the digital control block.
The digital control block takes the analog comparator input
and the main clock signal from the oscillator to provide the
appropriate pulses to the HIDRV and LODRV output pins.
These two outputs control the external power MOSFETs.
There is an additional comparator in the analog control sec-
tion whose function is to set the point at which the FAN5056
current limit comparator disables the output drive signals to
the external power MOSFETs.
High Current Output Drivers
The FAN5056 contains two identical high current output
drivers that utilize high speed bipolar transistors in a push-
pull conguration. The drivers’ power and ground are sepa-
rated from the chip’s power and ground for switching noise
immunity. The power supply pin, VCCP, is supplied from an
external 12V source through a series resistor. The resulting
voltage is sufcient to provide the gate to source drive to the
external MOSFETs required in order to achieve a low
RDS,ON.
Internal Voltage Reference
The reference included in the FAN5056 is a precision band-
gap voltage reference. Its internal resistors are precisely
trimmed to provide a near zero temperature coefcient (TC).
Based on the reference is the output from an integrated 5-bit
DAC.
In the FAN5056V90, the DAC monitors the 5 voltage identi-
cation pins, VID0-4, and scales the voltage linearly from
1.100V to 1.850V in 25mV steps. The code 11111 turns the
FAN5056A off.
In the FAN5056V85, the DAC monitors the 5 voltage identi-
cation pins, VID0-3 and VID25mV, and scales the voltage
from 1.050V to 1.825V in 25mV steps according to Table II.
Power Good (PWRGD)
The FAN5056 Power Good function is designed in accor-
dance with VRM8.5 and VRM9.0 DC-DC converter speci-
cations and provides a continuous voltage monitor on the
VFB pin. The circuit compares the VFB signal to the VREF
voltage and outputs an active-low interrupt signal to the CPU
should either of two conditions obtain: 1) any of the linear
power supply voltages deviate more than ±10% from their
nominal setpoint; 2) The switching power supply output is
more than +14% from (VVID + 80mV), or less than –14%
from (VVID – 120mV). The Power Good ag provides no
other control function to the FAN5056.
Output Enable/Soft Start (ENABLE/SS)
The FAN5056 will accept an open collector/TTL signal for
controlling the output voltage. The low state disables the out-
put voltage. When disabled, the PWRGD output is in the low
state.
Even if an enable is not required in the circuit, this pin
should have attached a capacitor (typically 100nF) to soft-
start the switching.
Over-Voltage Protection
The FAN5056 continuously monitors the output voltage for
protection against over-voltage conditions. If the voltage at
the VFB pin exceeds approximately 2.5V, an OVP circuit
forces the low-side MOSFET on, over-riding all other
conditions. The OVP circuit remains active, and the low-side
MOSFET remains on, until the VFB voltage drops below
approximately 2.1V. The OVP circuit is functional even
during startup; thus, protection is provided even during
startup with a shorted high-side MOSFET.
Oscillator
The FAN5056 oscillator section uses a xed frequency of
operation of 300KHz.
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