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参数资料
| 型号： | FAN5056V90M |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 8/19页 |
| 文件大小： | 266K |
| 代理商： | FAN5056V90M |
FAN5056V85/FAN5056V90
16
REV. 0.8.0 1/31/01
Pr
eliminar
y
Specication
of 30A and a 10m
sense resistor, use R
D = 14.4K * 30A *
10m
/(120mV * 18) = 2K. Further details on use of the
Programmable Active Droop may be found in Applications
Bulletin AB-24.
Remote Sense
The FAN5056 offers remote sense of the output voltage to
minimize the output capacitor requirements of the converter.
It is highly recommended that the remote sense pin, Pin 8, be
tied directly to the processor power pins, so that the effects
of power plane impedance are eliminated. Further details on
use of the remote sense feature of the FAN5056 may be
found in Applications Bulletin AB-24.
Adjusting the Linear Regulators’ Output
Voltages
Any or all of the linear regulators’ outputs may be adjusted
high to compensate for voltage drop along traces, as shown
in Figure 7.
Figure 7. Figure 7. Adjusting the Output Voltage of the
Linear Regulator
The resistor value should be chosen as
For example, to get the VTT voltage to be 1.50V instead of
1.20V, use R = 2K
* [(1.50/1.20) – 1] = 500.
Using the FAN5056 for Vnorthbridge = 1.8V
Similarly, the FAN5056 can also be used to generate Vnorth-
bridge = 1.8V by utilizing the AGP regulator as shown in
Figure 7: tie the TYPEDET pin to ground, and use R = 399
.
PCB Layout Guidelines
Placement of the MOSFETs relative to the FAN5056 is
critical. Place the MOSFETs such that the trace length of
the HIDRV and LODRV pins of the FAN5056 to the FET
gates is minimized. A long lead length on these pins will
cause high amounts of ringing due to the inductance of the
trace and the gate capacitance of the FET. This noise
radiates throughout the board, and, because it is switching
at such a high voltage and frequency, it is very difcult to
suppress.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the FAN5056. That
is, traces that connect to pins 1, 2, 23, and 24 (HIDRV,
SW, LODRV and VCCP) should be kept far away from the
traces that connect to pins 3, 20 and 21.
Place the 0.1F decoupling capacitors as close to the
FAN5056 pins as possible. Extra lead length on these
reduces their ability to suppress noise.
Each VCC and GND pin should have its own via to the
appropriate plane. This helps provide isolation between
pins.
Place the MOSFETs, inductor, and Schottky as close
together as possible for the same reasons as in the rst
bullet above. Place the input bulk capacitors as close to
the drains of the high side MOSFETs as possible. In
addition, placement of a 0.1F decoupling cap right on
the drain of each high side MOSFET helps to suppress
some of the high frequency switching noise on the input
of the DC-DC converter.
Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU will allow the parasitic resistance of the board traces
to degrade the DC-DC converter’s performance under
severe load transient conditions, causing higher voltage
deviation. For more detailed information regarding
capacitor placement, refer to Application Bulletin AB-5.
A PC Board Layout Checklist is available from Fairchild
Applications. Ask for Application Bulletin AB-11.
Additional Information
For additional information contact your local Fairchild
Semiconductor representative, or visit us at our web site
www.fairchildsemi.com.
VFB
VGATE
VOUT
10K
R
R2K
*
Vout
Vnom
=
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