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参数资料
| 型号： | FAN5061M |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 11/18页 |
| 文件大小： | 149K |
| 代理商： | FAN5061M |
FAN5061
2
Pr
eliminar
y
Specication
source with minimal external circuitry. Synchronous-mode
operation offers optimum efciency over the entire specied
output voltage range. An on-board precision low TC reference
achieves tight tolerance voltage regulation without expensive
external components, while Active Droop permits exact tailor-
ing of voltage for the most demanding load transients. The
FAN5061 includes linear regulator controllers for Vtt termina-
tion (1.5V), and Vclock (2.5V), each adjustable with an exter-
nal divider. The FAN5061 also offers integrated functions
including Power Good, Output Enable/Soft Start and current
limiting, and is available in a 20 pin SOIC package.
Pin Assignments
20
19
18
17
16
15
14
13
12
11
FAN5061
HIDRV
SW
GNDA
VID4
VID3
VID2
VID1
VID0
VTTGATE
VTTFB
VCCP
LODRV
GNDP
VCCA
VFB
IGB
PWRGD
SS/ENABLE
VCUFB
VCUGATE
1
2
3
4
5
6
7
8
9
10
Pin Denitions
Pin
Number Pin Name
Pin Function Description
1
HIDRV
High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel
MOSFET. The trace from this pin to the MOSFET gate should be <0.5".
2SW
High side Driver Source and Low side Driver Drain Switching Node. Together with
DROOP and ILIM pins allows FET sensing for Vcc current.
3
GNDA
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
4-8
VID0-4
Voltage Identification Code Inputs. These open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 2. Pull-up resistors are
internal to the controller.
9
VTTGATE
Gate Driver for VTT Transistor. For 1.5V output.
10
VTTFB
Voltage Feedback for VTT.
11
VCKGATE
Gate Driver for VCK Transistor. For 2.5V output.
12
VCKFB
Voltage Feedback for VCK.
13
ENABLE/SS
Output Enable. A logic LOW on this pin will disable all outputs. An internal current source
allows for open collector control. This pin also doubles as soft start for all outputs.
14
PWRGD
Power Good Flag. An open collector output that will be logic LOW if any output voltage
is not within ±12% of the nominal output voltage setpoint.
15
IFB
Vcc Current Feedback. Pin 15 is used in conjunction with pin 2 as the input for the Vcc
current feedback control loop. Layout of these traces is critical to system performance.
See Application Information for details.
16
VFB
Vcc Voltage Feedback. Pin 16 is used as the input for the Vcc voltage feedback control
loop. See Application Information for details regarding correct layout.
17
VCCA
Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor.
18
GNDP
Power Ground. Return pin for high currents flowing in pin 20 (VCCP).
19
LODRV
Vcc Low Side FET Driver. Connect this pin through a resistor to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should
be <0.5".
20
VCCP
Power VCC. For all FET drivers. Connect to system 12V supply through a 33
, and
decouple with a 1F ceramic capacitor.
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