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参数资料
| 型号： | FAN5365UC03X |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.84 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, PBGA9 |
| 封装： | 1.27 X 1.29 MM, 0.40 MM PITCH, WLCSP-9 |
| 文件页数： | 11/24页 |
| 文件大小： | 1014K |
| 代理商： | FAN5365UC03X |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5365 Rev. 1.0.4
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Positive Transitions
When transitioning to a higher VOUT, the regulator can
perform the transition using multi-step or single-step mode.
Multi-Step Mode:
The internal DAC is stepped at a rate defined by DEFSLEW,
CONTROL2[2:0], ranging from 000 to 110. This mode
minimizes the current required to charge COUT and thereby
minimizes the current drain from the battery when
transitioning. The PWROK bit, CONTROL2[5], remains LOW
until about 1.5
μs after the DAC completes its ramp.
VLOW
VHIGH
VSEL
VOUT
PWROK
t
POK(L-H)
Figure 36. Multi-Step VOUT Transition
Single-Step Mode:
Used if DEFSLEW, CONTROL2[2:0] = 111. The internal
DAC is immediately set to the higher voltage and the
regulator performs the transition as quickly as its current limit
circuit allows, while avoiding excessive overshoot.
Figure 37 shows single-step transition timing. tV(L-H) is the
time it takes the regulator to settle to within 2% of the new
setpoint, typically 7
μs for a full-range transition. The PWROK
bit, CONTROL2[5], goes LOW until the transition is complete
and VOUT settled. This typically occurs ~2μs after tV(L-H).
It is good practice to reduce the load current before making
positive VSEL transitions. This reduces the time required to
make positive load transitions and avoids current–limit-
induced overshoot.
t
V(L-H)
VLOW
VHIGH
98% VHIGH
VSEL
VOUT
PWROK
t
POK(L-H)
Figure 37. Single-Step VOUT Transition
All positive VOUT transitions inhibit PFM until the transition is
complete, which occurs at the end of tPOK(L-H).
Negative Transitions
When moving from VSEL = 1 to VSEL = 0, the regulator enters
PFM mode, regardless of the condition of the MODE bits,
and remains in PFM until the transition is complete. Reverse
current through the inductor is blocked, and the PFM
minimum frequency control inhibited, until the new setpoint is
reached; at which time, the regulator resumes control using
the mode established by MODE_CTRL. The transition time
from VHIGH to VLOW is controlled by load current and output
capacitance as:
LOAD
LOW
HIGH
OUT
)
L
H
(
V
I
V
C
t
=
(3)
VHIGH
VSEL
VOUT
PWROK
t
POK(L-H)
t
V(L-H)
VLOW
Figure 38. Negative VOUT Transition
Protection Features
Current Limit / Auto-Restart
The regulator includes cycle-by-cycle current limiting, which
prevents the instantaneous inductor current from exceeding
the “PMOS Current Limit” threshold.
The IC enters “fault” mode after sustained over-current. If
current limit is asserted for more than 32 consecutive cycles
(about 20
μs), the IC returns to shutdown state and remains
in that condition for ~80
μs. After that time, the regulator
attempts to restart with a normal soft-start cycle. If the fault
has not cleared, it shuts down ~20
μs later.
If the fault is a short circuit, the initial current limit is ~30% of
the normal current limit, which produces a very small drain
on the system power source.
Thermal Protection
When the junction temperature of the IC exceeds 150°C, the
device turns off all output MOSFETs and remains in a low
quiescent current state until the die cools to 130°C before
starting a normal soft-start cycle.
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